Senior Engineer, ASIC Digital Design (System IP Verification)

Job Title

Senior Engineer, ASIC Digital Design (System IP Verification)

Role Summary

Join the System IP Verification team in Hsinchu to verify configurable system-level IP and subsystems for next-generation RISC-V processor platforms, including coherent memory subsystems, interconnect, low-power and SoC infrastructure IP.

This role focuses on verification planning, SystemVerilog/UVM-based testbench development, simulation/regression, coverage-driven verification, automation and cross-team collaboration with architecture, RTL design, modeling, formal, software and system validation teams.

Experience Level

Senior - no specific years provided; role expects demonstrated technical capability and independent contribution.

Responsibilities

Primary verification and debugging responsibilities:

• Understand block and subsystem architecture; contribute to specification reviews and verification plans.
• Develop and maintain verification IP: tests, sequences, monitors, scoreboards, assertions, checkers and functional coverage using SystemVerilog/UVM or equivalent methodologies.
• Run simulations and regressions; analyze logs, waveforms and coverage; isolate root causes across RTL, testbench, protocol, configuration, clock/reset and subsystem-interaction boundaries.
• Automate test generation, regression flows and analysis using Python, C/C++ or shell scripting.
• Collaborate with architecture, RTL design, formal, modeling, software and system validation teams to resolve issues and meet quality and milestone objectives.
• Document verification intent, implementation, results and lessons learned; participate in technical reviews and knowledge sharing.

Requirements

Must-have technical skills and capabilities; preferred items listed below.

• Must-have: Hands-on experience with Verilog/SystemVerilog, C/C++ or Python for verification or modeling.
• Must-have: Practical understanding of RTL design, simulation and debugging; ability to analyze technical problems systematically.
• Must-have: Experience with simulation/regression environments, coverage analysis and debug workflows.
• Must-have: Clear written and spoken English communication; ability to work constructively with engineers across functions and geographies.
• Nice-to-have: Exposure to SystemVerilog/UVM, constrained-random verification, assertions/SVA, functional or code coverage, or formal verification.
• Nice-to-have: Familiarity with Linux, Git and EDA simulation or debug tools (VCS/Verdi, Xcelium/SimVision, Questa, Verilator or equivalents).
• Nice-to-have: Project, internship or research experience with processor architecture, RISC-V, cache or memory systems, interconnect/NoC, FPGA or SoC integration.
• Nice-to-have: Experience applying scripting to verification automation, test generation and regression analysis.

Education Requirements

Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science or a closely related field. Strong academic foundation expected in digital logic, digital IC design, computer architecture, VLSI or embedded systems. No certifications were specified; thesis/research or internship experience is listed as preferred experience.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.