Senior Engineer, Analog Layout

Job Title

Senior Engineer, Analog Layout

Role Summary

Responsible for analog physical layout and parasitic optimization for high-speed SerDes, broadband analog, ADC/DAC, PLL/DLL, and clock distribution blocks in advanced CMOS processes. Works with global design teams to iterate layouts, run verifications, and deliver tape-outs ready for volume production.

Experience Level

Senior. Typical experience: Bachelors +5+ years professional experience, or Master’s +2+ years (see Education Requirements for details).

Responsibilities

Key responsibilities include:

• Create and optimize analog/custom IC layouts from chip planning through tape-out.
• Run layout simulations and verifications (parasitic extraction, LVS/DRC/ERC) and debug issues with designers.
• Interpret and act on CALIBRE (DRC/LVS/ERC) reports to meet sign-off criteria.
• Collaborate with global cross-functional teams and paired designers; provide technical updates and presentations.
• Mentor junior layout engineers and contribute to layout team best practices.
• Support top-level integrations and readiness for volume production.

Requirements

Must-have technical skills and experience:

• Proven record of laying out high-performance analog circuits in state-of-the-art CMOS and delivering products to volume production.
• Deep understanding of layout methodology, parasitic optimization, and tape-out flow.
• High proficiency with layout entry tools (Cadence Virtuoso or Synopsys layout tools).
• Ability to analyze and resolve complex layout verification issues and report results clearly in English.
• Strong technical and analytical problem-solving skills.
• Preferred: experience with advanced process technologies and FinFET nodes.
• Nice-to-have: scripting/programming experience (Skill, Ample, Perl, or similar).

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering or a related field with at least 5+ years of related professional experience; or a Master’s degree in Computer Science, Electrical Engineering or a related field with 2+ years of professional experience.

Competitive compensation and benefits offered.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.