Senior Engineer, Analog Layout

Job Title

Senior Engineer, Analog Layout

Role Summary

The Senior Analog Layout Engineer will develop and deliver circuit- and block-level layouts for power-management ICs (PMICs), linear and switching DC-DC converters. The role works within the Power Business Unit and requires close collaboration with circuit designers, CAD/PDK/process engineering and multi-site teams to meet performance, area and yield targets.

This is an execution-focused role with opportunities to influence layout methodology and automation for a large power product portfolio.

Experience Level

Senior — requires at least 3+ years of professional experience in analog layout design and related flows.

Responsibilities

Accountable for floorplanning, layout implementation, verification, automation and knowledge transfer to junior engineers.

• Drive floorplan development and review to ensure optimal cell dimensions, device placement and pin locations.
• Implement layout using techniques for matching accuracy, parasitic reduction and yield optimization.
• Perform routing and verification (DRC, ERC, LVS) at block and circuit levels.
• Develop and use automation and scripts to improve turnaround times (TCL, Perl, or similar).
• Conduct and organize layout reviews; report progress and schedule estimates to management.
• Collaborate with CAD/PDK/process engineering to resolve tool, PDK or process issues.
• Mentor junior layout engineers and contribute to methodology and portability of IP across designs.
• Propose and implement improvements to layout methodology and procedures.

Requirements

Key technical and behavioral requirements. Items listed as "Must-have" are mandatory for consideration.

• Must-have: Minimum 3+ years of analog layout design experience and familiarity with layout flows; strong experience with deep-submicron CMOS layout techniques and parasitic-aware design.
• Must-have: Proficiency with relevant CAD tools and flows such as Virtuoso XL and Calibre (DRC, LVS, PEX); familiarity with VCAR / VSR / PVS / R3D or equivalent tools.
• Must-have: Strong scripting/automation skills (TCL, Perl, or similar) to improve throughput and tool flows.
• Must-have: Proven experience with routing, verification and layout-for-yield practices.
• Must-have: Ability to work independently on straightforward tasks, exercise judgment within defined procedures, and collaborate in multisite/multicultural teams; strong verbal and written English.
• Must-have: Flexible to undertake occasional international travel on short notice.
• Nice-to-have: Hands-on experience with PMICs, linear and switching DC-DC converters; prior mentoring experience; demonstrated improvements to layout methodology.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.