Senior Distinguished Engineer

Job Title

Senior Distinguished Engineer

Role Summary

Senior Distinguished Engineer in the Network Switch Business Unit (NSBU), responsible for defining and driving architecture for next-generation, high-performance switch ASICs used in AI, hyperscale cloud, carrier, and enterprise networks.

Lead cross-functional technical efforts from concept to silicon, own product architecture and validation activities, and influence long-term architectural roadmaps and system-level tradeoffs.

Experience Level

Senior — requires extensive industry experience. The role specifies 15+ years of experience in ASIC architecture and design, with a record of leading complex ASIC or multi-die products from concept through delivery.

Responsibilities

Primary responsibilities include technical leadership, architecture definition, and cross-functional delivery for advanced networking ASIC platforms.

• Define long-term architectural roadmaps and serve as principal architect for advanced networking ASICs focused on performance, scale, and power efficiency.
• Own product architecture definition, feature and protocol specification, and system-level tradeoff analysis.
• Develop and oversee behavioral and performance modeling, architecture validation, and performance analysis.
• Drive cross-functional collaboration with ASIC design, SerDes, firmware, validation, packaging, systems engineering, and product teams from concept to silicon and production.
• Represent architecture in executive technical reviews and customer engagements.
• Mentor and develop engineering talent; promote engineering rigor and innovation across teams.

Requirements

Must-have technical skills, experience, and other employment considerations.

• 15+ years in ASIC architecture and design with leadership experience delivering complex ASIC or multi-die products.
• Deep expertise in system-level architecture for networking ASICs, including high-performance switching pipelines, memory subsystems, packet processing, traffic management, and buffer management.
• Strong knowledge of Layer 2 / Layer 3 forwarding, QoS, congestion management, and networking protocols.
• Experience with Ethernet I/O subsystems (IEEE 802.3 MAC/PCS/FEC) and SerDes technologies.
• Proven skills in behavioral and performance modeling, architectural validation, and system-level tradeoff analysis.
• Strong understanding of system software interaction and control-plane integration implications.
• Proven communication skills and ability to present complex architectural concepts to executives and customers.
• Demonstrated mentoring and leadership capability in engineering organizations.
• Ability to work full-time onsite in Santa Clara for close collaboration with silicon and systems teams.
• Eligibility to access export-controlled technology as required by U.S. export regulations.

Nice-to-have:

• Industry-recognized contributions such as patents or publications.
• Experience with hyperscale AI clusters, cloud datacenter architectures, or multi-die/high-performance SoCs.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is required. A Master’s degree or Ph.D. is strongly preferred.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.