Senior Director, Silicon Architecture and Design Engineering (PCIe)

Job Title

Senior Director, Silicon Architecture and Design Engineering (PCIe)

Role Summary

Lead the PCIe Center of Excellence and own PCIe technology across Altera's programmable device portfolio, defining architecture, IP delivery, compliance, and customer enablement. Serve as the senior people leader and technical authority for high-speed interconnect, setting direction for PCIe and adjacent coherent interconnects.

The role requires cross-functional program leadership across architecture, design, verification, product engineering, and external partners to deliver production silicon for AI, cloud, networking, and edge markets.

Experience Level

Senior - requires extensive executive-level and hands-on technical experience (posting specifies 15+ years in silicon engineering and 10+ years in PCIe/high-speed I/O).

Responsibilities

Lead the team, define technical strategy, and drive execution of large silicon programs and PCIe technology across products.

• Lead, hire, mentor, and scale a high-performing silicon engineering organization including engineering managers and senior technical leads.
• Own delivery of FPGA, ASIC, and SoC products across the full silicon lifecycle: product definition, architecture, RTL design, verification, DFT, emulation, implementation, bring-up, validation, and production ramp.
• Drive scalable design methodologies, KPI-based execution frameworks, and automation to improve quality, predictability, and velocity.
• Set PCIe technical direction across controller, PHY/SerDes integration, DMA, virtualization, and related software/firmware co-design.
• Define architecture and integration strategy for PCIe and adjacent coherent interconnects (e.g., CXL) aligned to data-center and AI system needs.
• Establish verification, validation, compliance, and interoperability strategy from pre-silicon verification and emulation through post-silicon bring-up.
• Manage planning, prioritization, resource alignment, milestone tracking, and risk management for large, complex silicon programs.
• Represent silicon engineering in executive reviews and roadmap planning; engage customers, ecosystem partners, and standards organizations.

Requirements

Must-have technical experience and leadership capabilities; preferred items listed separately.

Must-have

• 15+ years in silicon engineering, ASIC/SoC development, or FPGA product development.
• 10+ years hands-on experience with PCIe and high-speed I/O technologies, including architecture and silicon/product development for compute, storage, networking, or data-center infrastructure.
• Deep practical expertise across PCIe Transaction, Data Link, and Physical layers, including link initialization/training, ordering, flow control, enumeration, power management, and error handling.
• Experience integrating PCIe controller and PHY subsystems into complex SoCs (endpoint and/or root-port architectures) and system integration.
• Experience delivering PCIe Gen4 and/or Gen5 designs into production silicon.
• Proven experience leading engineering managers and senior technical leads and delivering features through the full silicon lifecycle.
• Experience with verification, emulation, post-silicon bring-up, compliance testing, and interoperability activities.
• Ability to engage with customers, IP/EDA/foundry partners, and standards bodies; eligible for any required U.S. export authorizations.

Nice-to-have

• Experience with PCIe Gen6/Gen7 architectures and advanced PHY/SerDes technologies (PAM4, FLIT mode, FEC, advanced link training and equalization).
• Advanced PCIe features such as SR-IOV, ATS, PASID, PRI, IOMMU integration, peer-to-peer, advanced error handling/RAS, and security.
• CXL architecture and related coherency/memory expansion technologies.
• Experience with PCI-SIG compliance/interoperability processes and ecosystem interoperability across CPU, GPU, NIC, SSD, switch, and retimer devices.
• Background in FPGA architectures, programmable logic devices, or heterogeneous SoC platforms and IP reuse across device families.
• Knowledge of adjacent interconnects (e.g., UCIe, Ethernet) and silicon security primitives.

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Preferred: Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science. The posting pairs the required bachelor’s degree with 15+ years of relevant experience. No specific certifications were listed.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.