Senior Digital Verification Engineer - Contract

Job Title

Senior Digital Verification Engineer (Contract)

Role Summary

Contract senior verification engineer responsible for owning verification of complex SoC blocks and subsystems, including the company's proprietary Fabric technology. You will join the Verification & Emulation team and work closely with RTL designers and architects to build and extend UVM-based environments and drive coverage to sign-off.

Experience Level

Senior - requires 8+ years of ASIC/SoC design verification experience, with several projects taken from testbench development through tapeout.

Responsibilities

Primary responsibilities from spec through coverage sign-off:

• Own verification of assigned blocks and subsystems from specification review through coverage closure.
• Write and review verification plans with design and architecture leads.
• Architect, build, or extend UVM/SystemVerilog testbenches: agents, scoreboards, reference models, sequences, and constrained-random tests.
• Develop SystemVerilog assertions (SVA) and functional coverage models and drive functional and code coverage to closure.
• Debug complex simulation failures and coordinate root-cause and fixes with RTL designers.
• Report verification status, risks, and coverage gaps to the DV lead and design team.
• Document testbench environments for handoff and maintenance by the full-time team.

Requirements

Must-have technical skills and experience:

• Expert in UVM testbench architecture and SystemVerilog for verification (classes, constraints, interfaces, functional coverage, assertions).
• Proven track record driving functional and code coverage to sign-off on large multi-million-gate designs.
• Strong debugging skills with industry-standard tools (VCS/Verdi, Xcelium, or Questa).
• Proficiency in Python for regression automation, log analysis, and coverage post-processing.
• Ability to ramp quickly on new designs and deliver with minimal supervision; clear written and verbal communication.

Nice-to-have:

• C/C++ for reference modeling or SoC-level tests and DPI integration.
• Formal verification experience (e.g., JasperGold).
• Experience with agentic AI flows for DV (automated regression triage or failure debug).
• Background in computer architecture, spatial/dataflow architectures, or ML accelerators.
• Power-aware verification experience (UPF).

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.