Senior Digital Verification Engineer

Job Title

Senior Digital Verification Engineer

Role Summary

Join the digital verification team responsible for verifying complex digital and mixed-signal IP and full-chip designs for magnetic position/current sensors, motor drivers, and power-management ICs.

The role focuses on developing verification plans and testbenches to ensure first-pass silicon success for products used in e-mobility, clean energy, automation, and robotics.

Experience Level

Senior - the role title indicates senior level experience and responsibility.

Responsibilities

Primary verification responsibilities for block, subsystem, and full-chip levels, including mixed-signal interactions.

• Develop and execute verification plans for digital and mixed-signal IP and full-chip designs.
• Build and maintain constrained-random, coverage-driven SystemVerilog/UVM testbenches.
• Define functional coverage, assertions (SVA), and checkers; track coverage closure and bug metrics.
• Perform block-level, subsystem, and top-level verification including analog/digital interaction (Verilog-AMS / real-number modeling).
• Debug verification failures in collaboration with RTL designers, analog designers, and firmware teams.
• Contribute to regression setup, automation, and CI verification flows.
• Participate in design and verification reviews and sign-off readiness assessments.

Requirements

Must-have technical skills and tools for immediate contribution; preferred items listed separately.

Must-have:

• Strong proficiency in SystemVerilog and UVM methodology.
• Solid understanding of digital design fundamentals, RTL (Verilog/VHDL), and synthesis concepts.
• Experience with constrained-random, coverage-driven verification and assertion-based verification (SVA).
• Proficiency with industry simulation/debug tools (e.g., Cadence Xcelium/SimVision, Synopsys VCS/Verdi, or equivalent).
• Scripting skills for automation (Python, Perl, Tcl, or shell).
• Strong problem-solving, debugging, and communication skills; able to collaborate across RTL, analog, and firmware teams.

Nice-to-have:

• Mixed-signal verification experience (Verilog-AMS, real-number modeling / wreal).
• Familiarity with functional safety (ISO 26262) and/or automotive quality (AEC-Q100).
• Exposure to formal verification methods and tools.
• Experience with low-power verification (UPF/CPF).
• Knowledge of sensor, motor driver, or power-management IC architectures.
• Experience with version control (Git) and CI/CD for verification regressions.

Education Requirements

Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering (or equivalent practical experience) was specified.

About the Company

Company: Allegro MicroSystems

Headquarters: Manchester, New Hampshire, USA

Global semiconductor company with over 30 years of innovation, developing semiconductor devices and design enablement tools. Allegro focuses on device development, foundry partnerships, IP characterization, and design automation to support product roadmaps and technology advancement.