Senior Digital PD Engineer

Job Title

Senior Digital PD Engineer

Role Summary

Senior engineer responsible for end-to-end digital physical design and implementation for high-speed mixed-signal communication products. The role works on RTL-to-GDSII flows, timing closure, PPA optimization and physical verification while collaborating closely with analog, library, memory and IP teams.

Position reports to a product-development organization focused on custom IC system solutions and involves technical leadership, cross-functional coordination, and customer-facing engagement on implementation decisions.

Experience Level

Senior - requires extensive experience; posting specifies 12+ years of hands-on experience in Physical Design / Digital Backend implementation.

Responsibilities

Responsible for technical ownership of digital backend implementation and contributing to methodology and customer engagements.

• Drive full physical-design flow: floorplanning, placement, clock-tree synthesis (CTS), routing, and full-chip implementation.
• Perform Static Timing Analysis (STA) and ensure closure for timing, EM, IR drop, and physical verification (DRC/LVS).
• Optimize power, performance, and area (PPA) through aggressive implementation techniques.
• Implement and verify clock, reset, and DFT architectures for robust silicon operation.
• Develop and execute RTL coding, simulation, synthesis, and timing closure related to backend needs.
• Debug and evaluate designs at both circuit and behavioral levels; prepare test methods and specifications.
• Collaborate with analog, library, memory, and IP teams to remove flow bottlenecks and align execution.
• Mentor engineers, define implementation standards, and contribute to methodology development and tool qualification.
• Present technical decisions and status to internal stakeholders and customers during design reviews.

Requirements

Must-have technical skills and experience for immediate contribution.

• 12+ years of hands-on experience in Physical Design / Digital Backend implementation.
• Proven expertise in RTL-to-GDSII flows using industry-standard EDA tools (Synopsys and/or Cadence toolchain).
• Deep knowledge of timing closure, power integrity, signal integrity, and physical verification (DRC/LVS/ERC).
• Strong understanding of process-node design rules and implementation constraints.
• Experience working with Library, Memory, and IP teams in a product development context.
• Demonstrated ability to own and deliver complex designs independently from specification through signoff.
• Strong written and verbal communication skills for technical presentations and customer interactions.

Nice-to-have:

• Hands-on mixed-signal experience (analog-digital co-design, guard-ring strategies, substrate coupling mitigation, mixed-signal floorplanning).
• Prior role as subject-matter expert, methodology lead, or technical architect with demonstrated flow definition.
• Scripting and flow development experience (Tcl, Python, Perl) and EDA tool qualification experience.
• Experience with DFT integration (scan insertion, BIST, boundary scan) and low-power techniques (multi-Vt, power gating, voltage islands).

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or VLSI Design (posting also lists Bachelor's Degree as degree level). No alternative "equivalent experience" language explicitly stated.

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.