Senior Digital Engineer

Job Title

Senior Digital Engineer

Role Summary

Design power- and area-optimized digital circuits for mixed-signal data conversion and power-management products in advanced process nodes. Lead digital RTL architecture, integration, and delivery through the full silicon lifecycle in collaboration with analog, verification, and P&R teams.

Experience Level

Senior - requires more than 5 years of digital design experience in areas such as wireless handheld, data conversion, or power management.

Responsibilities

Contribute across the mixed-signal digital design flow from micro-architecture through silicon bring-up and production support.

• Architect, design, and integrate low-power digital blocks and top-level modules that meet timing, area, and power goals.
• Write and deliver RTL (Verilog/SystemVerilog), generate timing constraints, and synthesize designs for target nodes.
• Integrate designs at block and top level; run RTL and gate-level simulations and assist with testbench debug.
• Collaborate with P&R teams to achieve timing closure, area targets, and power objectives.
• Support DFT strategy and test-case development; participate in design reviews and checklist completion.
• Work with analog and verification engineers to define pre-silicon test scenarios and AMS/behavioural models.
• Perform silicon evaluation, document errata, propose workarounds, and implement engineering changes as needed.

Requirements

Key skills and experience required and preferred for the role.

Must have:

• More than 5 years of digital design experience in wireless handheld, data conversion, or power-management domains.
• Fluent in Verilog/SystemVerilog for RTL digital CMOS design.
• Strong understanding of ASIC design methodology and block-/chip-level verification techniques.
• Experience with Lint, CDC, and RDC tools and proven ability to debug RTL and gate-level simulations.
• Effective written and verbal English communication skills and ability to work independently and in teams.
• Willingness to travel domestically or internationally on short notice.

Preferred:

• Experience with mixed-signal design methodologies and developing design constraints for hand-off to P&R.
• Experience with STA, timing closure, low-power techniques (including clock/power gating and UPF), and power analysis/optimization.
• Familiarity with advanced verification methodologies (UVM) and industry protocols such as AMBA or I2C.

Education Requirements

Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.