Senior Digital Engineer

Job Title

Senior Digital Engineer

Role Summary

Design and deliver front-end digital micro-architecture and RTL for power-management ASICs (PMICs), from specification through silicon validation. The role partners with analog, verification, P&R, and test teams to produce low-power, spec-compliant digital blocks.

Experience Level

Senior — the posting specifies 3–6 years of relevant experience; the title indicates a senior role.

Responsibilities

Primary responsibilities include architecture, RTL delivery and cross-team integration for power-management digital blocks.

• Define micro-architecture and digital/analog boundaries for PMIC digital blocks.
• Develop RTL (Verilog/SystemVerilog) and deliver gate-level netlist ready for silicon.
• Handle multi-clock-domain design and Clock Domain Crossing (CDC) cleanly.
• Lead or collaborate on logic synthesis, STA, power estimation and timing sign-off.
• Design OTP/MTP/Efuse controllers, register read/write paths, data buses and trimming interfaces.
• Implement low-power optimized digital blocks meeting functional and power constraints.
• Plan verification tests, extract features and develop verification test cases.
• Perform silicon debug, root-cause analysis and post-silicon fixes.
• Support DFT strategy and interface with Placement & Route team for digital hand-off and post-layout verification.
• Author clear technical specifications and documentation for delivered blocks.

Requirements

Must-have technical skills and experience; follow-on items are useful but not mandatory.

Must-have:

• 3–6 years experience in logic design, micro-architecture and RTL coding.
• Strong Verilog / SystemVerilog skills.
• Hands-on experience with power-product / PMIC digital design and mixed-signal environments.
• Experience with synthesis, STA, timing-constraint development and P&R sign-off.
• Proven ability to handle CDC, timing closure and low-power design constraints.
• Familiarity with OTP/MTP/Efuse, register interfaces and trimming flows.
• Familiarity with power-chip communication protocols (I2C, PMBus, SPI) and bus handling.
• Silicon debug experience and root-cause analysis skills.
• Experience supporting DFT implementation and collaboration with P&R teams.

Nice-to-have / Additional qualifications:

• Formal verification exposure and experience with power estimation tools.
• Ability to work across multi-site, multi-cultural teams and travel occasionally at short notice.

Education Requirements

Degree-level qualification in Electronics Engineering (e.g., Bachelor's / B.E. / B.Tech in Electronics or equivalent).

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.