Senior Digital Engineer

Job Title

Senior Digital Engineer

Role Summary

The Senior Digital Engineer will design and deliver RTL and microarchitecture for SoC-, subsystem- and block-level digital logic in Morse Micro's low‑power Wi‑Fi IoT chips. The role leads verification strategy, supports synthesis/QoR and P&R, and coordinates across analog, layout, DFT and software teams to achieve tapeout-ready silicon.

Relocation and visa support are available for successful overseas candidates.

Experience Level

Senior — typically 5+ years of relevant digital/SoC design experience.

Responsibilities

Primary responsibilities include:

• Implement SystemVerilog and Chisel RTL across chip, subsystem and block levels to meet PPA targets.
• Define microarchitecture and detailed design specifications; translate product and market requirements into technical requirements.
• Lead verification strategy and close test plans: RTL simulations, gate-level sims, X-prop, CDC/RDC analysis, linting and FPGA emulation.
• Architect clocking, reset and power domains; author UPF/CPF power intent and drive power-aware simulations.
• Apply low-power techniques appropriate for battery/energy-harvesting IoT devices and integrate mixed-signal IP, owning the digital/analog interface contract.
• Support synthesis QoR, P&R, ECO/LEC closure, gate-level and power-aware verification, and tapeout checklist completion.
• Drive improvements to digital design, verification infrastructure and automation tooling.
• Use AI coding assistants and agents for RTL, verification, scripting and documentation; identify and adopt AI opportunities for spec analysis, test generation, debug and automation.
• Coordinate cross-functionally to hit major project milestones and deliver large, complex projects on schedule.
• Mentor junior engineers and enforce coding standards, reviews and methodology improvements.

Requirements

Essential technical and professional requirements:

• 5+ years experience as a Senior Digital Engineer with proven delivery of complex digital blocks, subsystems or SoC architectures.
• Strong RTL and verification skills: Verilog/SystemVerilog and digital verification methodologies; C programming.
• Experience with synthesis flows, QoR, ECO implementation and debug; CDC/RDC analysis expertise.
• Proficiency in scripting and automation (Python, Tcl, Shell, Makefiles, or similar).
• Experience developing design automation and infrastructure.
• Excellent verbal and written communication, strong analytical/problem-solving skills, and ability to deliver under schedule pressure.

Desirable:

• Low-power design experience (clock gating, power gating, retention, isolation).
• Familiarity with embedded systems, bus or processor architectures.
• Experience integrating mixed-signal IP (ADPLL, PHY) and supporting P&R/DFT flows.

Education Requirements

BSc, MSc or PhD in Electrical, Electronics or Communications Engineering, or Computer Science; or equivalent practical experience.

About the Company

Company: Morse Micro

Headquarters: Sydney, New South Wales, Australia

Morse Micro is an Australian fabless semiconductor company developing low-power Wi‑Fi HaLow (802.11ah) chips and SoCs for Internet of Things (IoT) applications, with global offices supporting design, silicon bring-up and production.