Senior Digital Design Engineer, HBM

Job Title

Senior Digital Design Engineer, HBM

Role Summary

Design and deliver high-performance digital logic for HBM-related silicon, driving work from micro‑architecture through RTL implementation, synthesis support, and post‑silicon debug. The role interfaces with verification, physical design, CAD, DFT and system teams to achieve timing, power and functional goals.

Position sits within a cross‑functional ASIC/digital design team focused on memory and storage products; emphasis on robust, scalable RTL and design-for-closure practices.

Experience Level

Senior-level. The posting does not specify a required number of years of experience; candidates should have experience appropriate for a senior ASIC/digital design engineer.

Responsibilities

Key responsibilities include end-to-end digital design and delivery:

• Drive digital design lifecycle: concept, spec, RTL implementation, verification handoff, documentation, and post‑silicon debug support.
• Develop scalable, parameterized RTL in Verilog/SystemVerilog aligned to architectural specs.
• Define and refine micro‑architecture for logic blocks (FSMs, datapaths, FIFOs, pipelines, arbitration).
• Analyze tradeoffs across area, power, latency and throughput and document design decisions.
• Perform CDC/RDC analysis and apply robust clocking and reset strategies.
• Support synthesis and static timing analysis: generate/debug SDC constraints and interpret timing reports.
• Apply low‑power methodologies (CPF/UPF, clock gating, partitioning, isolation/level shifters).
• Collaborate with verification, DFT, physical design and CAD to achieve design closure and test readiness.

Requirements

Must-have technical skills and experience; concise list of core expectations.

• Strong RTL coding and design skills in Verilog/SystemVerilog.
• Practical micro‑architecture experience for datapaths, control logic, FIFOs and pipelines.
• Experience with synthesis flows and static timing analysis (SDC, timing report interpretation).
• CDC/RDC analysis experience and proven clock/reset strategies.
• Familiarity with low‑power design techniques (CPF/UPF, clock gating, multi‑domain partitioning).
• Experience collaborating with verification, DFT, physical design, and CAD teams; familiarity with scan/ATPG and formal/functional verification concepts.
• Experience diagnosing post‑silicon issues and supporting silicon bring‑up.

Nice-to-have:

• Experience with memory interfaces or HBM-related design.
• Familiarity with AI-enabled design assistance tools.
• Advanced formal verification, low-power closure, or extensive post‑silicon debug experience.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.