Senior Digital Design Engineer

Job Title

Senior Digital Design Engineer

Role Summary

Senior engineer responsible for synthesis and front-end implementation of digital IP blocks within ASIC/SoC projects. The role translates RTL into optimized gate-level netlists and works across RTL, DFT and physical-design teams to meet performance, power and area targets.

Experience Level

Senior — typically requires 5+ years of relevant digital ASIC/SoC design experience (synthesis/front-end focus).

Responsibilities

Key responsibilities include front-end implementation, timing closure, verification, power and area optimization, automation, and tool evaluation.

• Perform synthesis of RTL designs for digital blocks and subsystems, including hierarchical synthesis.
• Develop and implement timing constraints (SDC) to achieve target frequencies.
• Conduct static timing analysis (STA), identify critical paths, and drive timing closure with design teams.
• Execute formal equivalence checking (LEC) between RTL and synthesized netlists.
• Analyze and optimize front-end power using power analysis tools and UPF-aware techniques.
• Estimate and optimize area to meet chip size requirements.
• Collaborate with RTL designers, DFT engineers, and physical-design engineers for integration and hand-off.
• Develop and maintain automation scripts (Tcl, Python, Perl) for synthesis flows and analysis.
• Evaluate and integrate CAD tools and methodologies to improve flows and quality.
• Document design constraints, methodologies, and analysis results.

Requirements

Must-have technical skills and experience; items marked as nice-to-have where applicable.

• 5+ years of experience in digital ASIC/SoC design with a focus on synthesis and front-end implementation.
• Proficiency with industry synthesis tools (for example Synopsys Design Compiler, Fusion Compiler, or equivalent).
• Strong understanding of STA concepts and experience with tools such as Synopsys PrimeTime.
• Experience with formal verification tools (for example Synopsys Formality or Cadence Conformal).
• Understanding of UPF, low-power design techniques, and power analysis concepts.
• Solid knowledge of Verilog / SystemVerilog for digital design.
• Proficiency in scripting for automation (Tcl, Python, Perl).
• Excellent problem-solving skills, attention to detail, and effective communication across teams and time zones.
• Nice-to-have: Knowledge of DFT principles and experience integrating new CAD tools or methodologies.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.