Senior Digital Design and Verification Engineer

Job Title

Senior Digital Design and Verification Engineer

Role Summary

Own design and verification of parts of the digital IP portfolio that integrate Synthara's compute-in-memory technology (ComputeRAM®). Deliver synthesis-ready SystemVerilog RTL and UVM-based verification to achieve coverage closure and produce sign-off quality silicon.

Work closely with custom design, backend, and software teams to meet power, performance, area (PPA) targets and time-to-tapeout.

Experience Level

Senior — 5+ years in digital ASIC design or verification; posting indicates ~6 years of seniority.

Responsibilities

The role delivers RTL, verification environments, and sign-off artifacts for digital IP. Key responsibilities include:

• Implement synthesis-friendly SystemVerilog RTL: memory-mapped control blocks, AXI/AHB/APB bridges, FIFOs, arbiters, DMA, and datapaths with clear reset and CDC strategies.
• Optimize designs for power and area while meeting timing constraints.
• Develop UVM testbenches (agents, sequencers, predictors, scoreboards) and drive constrained-random and directed testing to close functional, code, and assertion coverage.
• Run gate-level simulations with SDF back-annotation for critical paths and support FPGA prototypes for early HW/SW bring-up.
• Produce specifications, register maps, programming models, and user/IP guides.
• Contribute reusable verification components and CI/regression infrastructure to increase pass-rate stability and reduce regression time.
• Collaborate across cross-functional teams to prepare lint/CDC/RDC clean sign-off packages and tapeout deliverables.

Requirements

Must-have:

• 5+ years of experience in digital design or verification for ASICs.
• Strong SystemVerilog RTL skills and practical UVM knowledge.
• Hands-on experience with RISC-V or ARM as an integrator or designer.
• Understanding of synthesis and how RTL choices affect timing, power, and area.
• Clear technical communication and habit of converting one-off designs into reusable components.

Nice-to-have:

• Experience with memory-adjacent IP (SRAM controllers, MBIST/scan) and power-aware/UPF flows.
• Familiarity with AMBA protocols (AXI/AHB/APB), clock/reset schemes, CDC handshakes, FIFOs, arbiters, and SVAs.
• GLS proficiency (SDF back-annotation) and FPGA bring-up experience.
• Python or Tcl for stimulus generation, log parsing, and coverage triage.
• Background in AI/DSP accelerators or quantized dataflows.

Education Requirements

Not specified.

About the Company

Company: Synthara

Headquarters: Zürich, Switzerland

Synthara develops ComputeRAM® hardware and software for efficient on-device AI, providing compilers, drivers, SDKs and tooling to enable AI workloads from microcontrollers to accelerators, with a focus on hardware/software co-design and developer usability.