Senior DFT - Silicon Validation Engineer

Job Title

Senior DFT - Silicon Validation Engineer

Role Summary

Join the Design-for-Test (DFT) and Silicon Validation team to lead silicon bring-up, debug, and yield ramp activities for complex SoCs. The role focuses on defining DFT architecture, accelerating post-silicon validation, and collaborating across hardware, firmware, and test teams to deliver production-ready chips.

Experience Level

Senior-level. Typical experience ranges from ~5 to 8+ years in DFT, silicon validation, or related domains depending on prior degree and responsibilities.

Responsibilities

Accountable for end-to-end silicon validation and DFT enabling activities:

• Define and drive DFT architecture, methodologies, and test strategies for ATE and production validation.
• Lead early silicon bring-up, characterization, and debugging for complex SoCs.
• Plan validation activities from architecture through productization and production ramp.
• Execute chip validation on ATE, develop and debug test content, and analyze silicon behavior under varied operating conditions.
• Identify root causes of failures and work with cross-functional teams to implement fixes and yield improvements.
• Drive yield ramp and waste-reduction initiatives across multiple products.
• Mentor and coordinate with teams to integrate DFT features into the product roadmap.

Requirements

Must-have skills and experience:

• Proven expertise in silicon debug, bring-up, and productization of DFT features.
• Hands-on experience with pre-silicon validation for DFT features and ATE-based chip validation.
• Demonstrated leadership in driving yield ramp and resolving production issues for multiple products.
• Strong debugging and failure-analysis skills for complex mixed-signal/digital SoCs.
• Strong scripting/programming skills (Perl, Python, Tcl or similar).
• Excellent written and oral communication skills and ability to work across functions.

Nice-to-have:

• Experience implementing advanced DFT methodologies and industry-standard DFT tools.
• Knowledge of high-speed protocols and semiconductor process technology.
• Track record of proactive problem solving on rare or complex silicon issues.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) with 8+ years, Master of Science in EE (MSEE) with 5+ years, or PhD with 3+ years in DFT or related domains are typical; equivalent practical experience is acceptable.

Additional Notes

Base salary ranges provided by the employer: USD 168,000–264,500 (Level 4) and USD 196,000–310,500 (Level 5). Role is based in Santa Clara, CA. NVIDIA is an equal-opportunity employer and uses automated tools in recruiting.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.