Senior DFT Engineers

Job Title

Senior DFT Engineers

Role Summary

Senior DFT engineer responsible for design-for-test implementation and verification across block and SoC levels. The role works with backend (BE) and validation teams to insert and optimize MBIST and scan, generate ATPG patterns, run verification and formal checks, and support firmware and hardware debug.

Experience Level

Senior. Years of experience not specified in the source posting.

Responsibilities

Primary technical responsibilities derived from the job posting:

• Analyze designs and plan top-level test pins for DFT integration.
• Insert and optimize MBIST and scan logic, including scan compression; validate scan insertion results.
• Generate DFT constraints for backend and PrimeTime; hand off post-DFT netlist and constraints to BE team.
• Run formal verification between synthesized netlist and post-DFT netlist.
• Develop validation plans and generate ATPG test patterns at block and SoC levels; perform SoC-level pattern re-targeting.
• Run ATPG, pattern verification, and pattern simulations (block and SoC); perform block-level timing simulation and MBIST RTL/gate-level validation.
• Execute full MBIST and scan pattern generation and verification pre- and post-layout; after top netlist availability, run block-level patterns from the top level.
• Monitor test coverage and pattern counts; optimize pattern sets and test flow.
• Develop firmware and APIs related to test/validation and perform hardware/system debug.

Requirements

Must-have technical skills and experience (education items moved to Education Requirements):

• Proven experience with DFT flows: MBIST and scan insertion, scan compression, and related validation.
• Experience generating ATPG test patterns and running ATPG on DFT-inserted netlists; familiarity with pattern simulation and timing simulation.
• Experience with formal verification between synthesized and post-DFT netlists and generating constraints for backend/PrimeTime.
• Experience handing off post-DFT netlist and constraints to backend teams and coordinating SoC-level integration.
• Firmware/API development experience and practical hardware/system debug skills.

Nice-to-have:

• Experience with SoC-level pattern re-targeting and large-block integration.
• Familiarity with ATPG/MBIST tool flows and scripting to automate pattern generation and validation.

Education Requirements

BTECH / MTECH (B.Tech or M.Tech) specified in the posting. No specific field of study or mention of equivalent-experience language was provided.

About the Company

Company: Digicomm Semiconductor

Digicomm Semiconductor is a company specializing in semiconductor design and test engineering services, focusing on DFT (Design for Test), MBIST, scan insertion, ATPG pattern generation, and verification for SoC and block-level designs.