Senior DFT Engineer (Tessent/IJTAG Specialist)
Encore SemiJob Title
Senior DFT Engineer (Tessent/IJTAG Specialist)
Role Summary
Architect and implement advanced design-for-test (DFT) solutions with a focus on customizing Siemens Tessent flows and authoring non-standard test sequences. The role supports pre-silicon pattern generation, gate-level simulation, and post-silicon bring-up and failure analysis for complex IP and hardware instruments.
Anticipated base salary: $130,000–$160,000 per year (plus benefits).
Experience Level
Senior — typically requires 5+ years of relevant DFT/ATPG experience and a track record of successful tape-outs.
Responsibilities
Primary responsibilities include:
- Author and edit ICL/PDL to implement custom test sequences for non-standard hardware instruments and complex IP.
- Integrate DFT and drive pattern generation using the Tessent Shell environment.
- Develop custom ATPG patterns and perform gate-level simulations (GLS) to validate test coverage.
- Support silicon bring-up, debug, and failure analysis using engineered test sequences.
Requirements
Must-have qualifications:
- Expert-level experience with the Siemens Tessent tool suite.
- Proven ability to customize PDL/ICL for non-standard test delivery.
- Strong background in Scan, ATPG, JTAG, and Hierarchical DFT methodologies.
- Proficiency in Tcl and Python for flow automation.
- Minimum 5 years of relevant experience with successful tape-outs.
- Work authorization: US citizen or Lawful Permanent Resident required.
Nice-to-have:
- Not specified.
Education Requirements
Not specified.
About the Company
Company: Encore Semi
US-based semiconductor engineering firm specializing in design-for-test (DFT), ATPG, Tessent flows, and silicon bring-up; provides engineering services and hires senior DFT specialists for remote US-based roles.
