Senior DFT Engineer - LPU

Job Title

Senior DFT Engineer - LPU

Role Summary

Join NVIDIA's AI hardware engineering team to design and implement Design-for-Test (DFT) architecture for next-generation AI chips. The role partners with architecture, physical design, STA, CAD methodology, and post-silicon teams to enable robust testability and silicon bring-up.

This position focuses on SCAN, MBIST, ATPG, JTAG debug, timing closure in DFT mode, test vector generation, and collaboration with lab/ATE teams for silicon debug and yield optimization.

Experience Level

Senior — typically requires 5+ years of industry experience in DFT for high-performance ASICs.

Responsibilities

Primary responsibilities include defining and delivering DFT structures, collaborating across teams, and supporting silicon bring-up and test optimization.

• Define and implement SCAN, MBIST, and JTAG debug structures and associated DFT architecture.
• Drive creation of ATPG and MBIST test vectors and translate test patterns for silicon deployment.
• Build DFT timing constraints and work with Physical Design and STA sign-off to achieve timing closure in DFT mode.
• Support post-silicon bring-up: debug and validate test patterns on silicon and ATE.
• Collaborate with CAD/methodology teams to introduce AI-driven optimizations and improve DFT implementation efficiency.
• Analyze yield data and contribute to test optimization and yield learning efforts.

Requirements

Key technical skills and practical experience required. Education details are summarized separately below.

• 5+ years practical experience in DFT for large SoC/ASIC designs (industry experience preferred).
• Hands-on experience with SCAN, MBIST, ATPG tools and test generation processes for large SoCs/ASICs.
• Domain expertise in ATPG, test pattern translation, scan compression, MBIST, yield learning, and LBIST.
• Familiarity with ATPG Streaming SCAN Network (SSN) implementation and UDFMs such as Cell Aware and Small Delay Defect.
• Experience working with real silicon in lab environments and debugging DFT test sequences on ATE.
• Solid understanding of RTL-to-GDS methodologies and formal equivalence checking.
• Strong scripting and coding skills (Tcl and Python).
• Excellent interpersonal and organizational skills; experience collaborating across physical design, STA, CAD, and post-silicon teams.
• Nice to have: prior work on AI-driven CAD optimizations or test automation frameworks.

Education Requirements

Bachelor's or M.S. in Computer Engineering, Electrical Engineering, or a related technical field — or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.