Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Responsible for defining and implementing design-for-test (DFT) architecture and flows for SoC projects. Works with product, test, CAD and physical-design teams to deliver production-ready test solutions and support post-silicon bring-up.

Focus areas include scan architecture, MBIST, boundary scan, ATPG, pattern simulation, and test methodology improvements.

Experience Level

Senior-level — 4–8 years of industry DFT experience.

Responsibilities

Primary responsibilities include DFT architecture, implementation, verification, and post-silicon support.

• Define DFT architecture: scan partitioning, compression, at-speed, IR, low-power strategies, MBIST and JTAG/boundary scan.
• Collaborate with product and test engineering to optimize test cost and coverage.
• Develop and maintain SCAN and MBIST insertion flows; handle hierarchical scan at block and top level.
• Create timing constraints for SCAN/MBIST modes and debug timing violations.
• Implement ATPG flows for various fault models and generate test patterns; perform SCAN, MBIST and boundary-scan pattern simulation.
• Provide solutions for testing analog macros and support test integration.
• Support post-silicon bring-up on ATE, perform failure analysis, and work on yield and test-cost improvement.
• Work closely with physical-design teams throughout development.
• Mentor new team members on flows, methodology and execution.

Requirements

Must-have skills and relevant experience; preferred items noted separately.

• Must-have: 4–8 years of industry DFT experience and a proven record of taking at least one product from architecture through production.
• Must-have: Hands-on post-silicon bring-up and debug experience.
• Must-have: Strong scripting skills (Perl, Python, Tcl) and solid command of HDLs.
• Must-have: Strong interpersonal and communication skills for cross-site collaboration.
• Nice-to-have: Experience with Mentor Tessent DFT tools (SCAN, MBIST, LBIST, OCC, EDT, SSN, boundary scan).
• Nice-to-have: Exposure to deep-submicron effects and low-power implementation using UPF/CPF.
• Nice-to-have: Experience with Cadence implementation tools (Genus, Tempus) and timing-closure/physical-design familiarity.
• Willingness to travel approximately 10% of the time.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.