Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Design-for-Test (DFT) engineer responsible for defining and implementing DFT architecture and delivering high-quality ATPG patterns and verification support across ASIC/SoC product lines. Works on methodology, flow automation, and provides pre- and post-silicon debug and silicon bring-up support.

Works independently and with cross-functional teams; mentors junior engineers and drives DFT innovation to achieve high coverage, low power, and low test time.

Experience Level

Senior level — typically 6–8 years of directly related ASIC/SoC DFT experience as indicated by the posting.

Responsibilities

Primary responsibilities include defining DFT architecture, implementing DFT features, and providing verification and silicon support:

• Define DFT specifications and architecture; implement DFT using current methodologies and tools.
• Develop and maintain DFT flows, automation, and methodology improvements.
• Deliver verified ATPG patterns with target high coverage, low power impact, and reduced test time.
• Perform pre-silicon and post-silicon verification, debug, failure analysis, and silicon test bring-up support.
• Perform scan insertion, compression insertion, on-chip clock control insertion, ATPG, and DFT verification tasks.
• Provide mentorship to junior team members and collaborate with peer organizations and cross-functional teams.
• Support test planning and on-chip test features such as MBIST and LBIST.
• Occasional travel required (approximately 10%).

Requirements

Must-have technical skills and experience, followed by preferred skills.

• Must-have: 6–8 years of ASIC/SoC DFT experience; expert knowledge of DFT architecture and planning.
• Hands-on experience with Tessent DFT tools; practical experience with scan, test compression, at-speed test, MBIST, and LBIST.
• Experience with scan insertion, compression insertion, on-chip clock-control insertion, ATPG, and DFT verification.
• Gate-level simulation with SDF and silicon test bring-up, failure analysis and diagnosis experience.
• Scripting proficiency in Perl, Python, or Tcl.
• Strong written and verbal communication skills and ability to work collaboratively in teams.
• Willingness to travel (~10%).
• Nice-to-have: Experience with Cadence and Synopsys DFT tools, IEEE 1149/JTAG, static timing analysis, BIST, synthesis and DFT insertion, and low-power scan/UPF techniques.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.