Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Senior engineer responsible for design-for-test (DFT) verification and production-test pattern development for mixed-signal IP and complex SoCs. The role leads pattern generation and bring-up on ATE, performs root-cause debugging from simulation to silicon, and works across DFT, design, verification, physical design, and test teams in pre- and post-silicon phases.

Experience Level

Senior - 10+ years of semiconductor industry experience with hands-on DFT and ATE work.

Responsibilities

Own DFT verification, pattern development and ATE bring-up for mixed-signal blocks and SoC-level features. Drive investigations to closure and work closely with cross-functional engineering teams.

• Perform DFT verification of mixed-signal IP blocks and SoC-level DFT features.
• Develop, validate, and debug ATE test patterns and drive pattern bring-up on silicon.
• Perform ATE pattern debug and stabilization; perform root-cause analysis of simulation-to-silicon and tester failures.
• Develop and maintain PDL for embedded instruments and iJTAG networks.
• Generate and debug DFT patterns using Siemens Tessent tools.
• Work with JTAG (IEEE 1149.1) and iJTAG (IEEE 1687) architectures and associated verification flows.
• Debug timing, protocol, pattern, and infrastructure issues across simulation and ATE environments.
• Collaborate with DFT, design, verification, physical design, product engineering, and test engineering teams.
• Drive technical issues independently from investigation through root-cause identification to resolution.

Requirements

Must-have technical skills and experience for immediate contribution, followed by relevant nice-to-have items.

• Must-have: 10+ years hands-on DFT experience, including DFT verification of mixed-signal blocks.
• Must-have: Strong knowledge of ATE architecture, test programs, pattern formats, pattern execution and debug flows; experience with pattern bring-up on silicon.
• Must-have: Proven experience with Siemens Tessent tools for pattern generation and PDL development.
• Must-have: In-depth understanding of JTAG and iJTAG protocols (IEEE 1149.1, IEEE 1687) and embedded instruments.
• Must-have: Strong analytical and problem-solving skills; ability to perform failure analysis and root-cause debugging.
• Must-have: Ability to take ownership, work independently, and communicate effectively with distributed teams.
• Nice-to-have: Experience with SCAN & MBIST, lane repair schemes, loopback test verification for high-speed SERDES/DDR/PCIe/USB, sensors calibration, and test-time reduction/optimization.

Education Requirements

Not specified.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.