Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

The Senior DFT Engineer will design, implement, and validate design-for-test solutions for digital ASIC/SoC projects. The role partners with RTL, design, verification, and test teams to enable scan insertion, ATPG, fault simulation, test compression, and silicon bring-up.

Primary mission: ensure chip testability, deliver test patterns and DFT sign-off artifacts, and support debug during bring-up.

Experience Level

Senior-level. Specific years of experience not specified.

Responsibilities

Key responsibilities include:

• Define and implement DFT architecture and scan strategies for digital designs.
• Perform scan insertion, ATPG, fault simulation, and compression flow implementation.
• Generate and validate test patterns to meet test coverage and quality targets.
• Collaborate with RTL, synthesis, timing, and validation teams to resolve testability issues.
• Analyze failing patterns, debug silicon test failures, and support silicon bring-up activities.
• Produce DFT deliverables and documentation and mentor junior engineers.

Requirements

Minimum and preferred qualifications:

• Must-have: Practical experience in DFT implementation and ATPG flows; familiarity with scan insertion, fault simulation, and test compression; experience with industry DFT/ATPG tools; scripting skills (TCL, Python, or similar); solid digital design and verification knowledge.
• Nice-to-have: Experience with BIST/JTAG, SoC/ASIC project workflows, silicon bring-up, and common EDA toolchains; prior mentorship or leadership on DFT deliverables.

Education Requirements

Not specified.

About the Company

Company: Arrow Electronics

Headquarters: Centennial, Colorado, United States

Global technology solutions provider that distributes electronic components and enterprise computing solutions, and offers design, engineering and supply-chain services through subsidiaries (including eInfochips). Serves industrial, commercial and government customers worldwide.