Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Work on Design-for-Test (DFT) architecture, verification and post-silicon validation for complex ASICs. The role is part of a DFT team responsible for test infrastructure across chip development and silicon bring-up.

Own implementation of test access mechanisms, IO and memory BIST, scan compression, and deploy DFT methodologies while collaborating with RTL, P&R, STA and validation teams.

Experience Level

Senior-level. Typical experience guidance from the posting: MSEE with 3+ years, BSEE with 5+ years, or a PhD in DFT or a related domain.

Responsibilities

Key responsibilities include design, verification, deployment and cross-functional coordination of DFT solutions.

• Design and implement test access mechanisms (TAM), IO BIST, memory BIST and scan-compression schemes.
• Develop and deploy DFT methodologies for next-generation products.
• Create and validate scan test plans, ATPG flows and fault simulation strategies for large, multi‑million‑gate designs.
• Verify and validate test patterns and test logic using vendor tools; analyze coverage and quality trade-offs.
• Collaborate with RTL, clock design, STA, place-and-route and power teams to balance testability, performance and cost.
• Support silicon debug and ATE bring-up, including pattern formats, failure processing and test program development.
• Mentor and guide junior engineers on test design decisions and trade-offs.

Requirements

Must-have technical skills and experience; separate nice-to-have items are noted.

• Must-have: Proven expertise in scan test plan definition, BIST (memory and IO), ATPG and fault simulation.
• Must-have: Experience verifying and validating test logic on complex, multi‑million‑gate designs using vendor EDA tools.
• Must-have: Experience in silicon debug and ATE bring-up, including failure analysis and test program development.
• Must-have: Cross-functional experience with RTL/clock design, STA, place-and-route and power to inform DFT trade-offs.
• Must-have: Strong written and oral communication skills.
• Nice-to-have: Strong scripting/programming skills in Perl, Python or Tcl to automate flows and tooling.

Education Requirements

The posting specifies BSEE (or equivalent practical experience) with 5+ years; MSEE with 3+ years; or a PhD in DFT or related domains. Equivalent practical experience is explicitly accepted.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.