Senior DFT Engineer
eInfochipsJob Title
Senior DFT Engineer
Role Summary
The Senior DFT Engineer implements and verifies design-for-test (DFT) solutions for advanced-node SoCs and IPs, primarily for networking applications. The role covers scan insertion, ATPG, MBIST, JTAG, pattern simulation, debug and silicon bring-up, and automation of DFT flows.
This position works within an ASIC/SoC engineering and test team to deliver testability, pattern generation, and debug support for multi-million-gate designs and silicon validation.
Experience Level
Senior — 5–7 years of hands-on DFT experience.
Responsibilities
Core responsibilities include implementing DFT features, generating and validating test patterns, debugging failures, and improving DFT flows and automation.
- Implement DFT for 3nm and 5nm networking chips and for IPs.
- Perform RTL checks for scan-insertion compatibility using static analysis tools.
- Execute scan-insertion workflows and manage scan chains.
- Generate ATPG patterns in compressed and uncompressed modes and perform pattern simulation with and without timing across corners.
- Debug mismatches and failures during simulation and silicon bring-up.
- Insert and verify MBIST at block and top levels; support silicon MBIST debug and bring-up.
- Insert and verify IEEE 1149.1 (JTAG) infrastructure.
- Develop and maintain automation and build flows (scripts, makefile targets) to improve DFT productivity.
- Collaborate with RTL, verification, and bring-up teams to resolve testability and silicon issues.
Requirements
Required skills and experience are listed below. Tools and additional skills that increase effectiveness are noted as nice-to-have.
- 5–7 years of direct DFT experience covering scan-insertion, ATPG, and pattern simulation.
- Hands-on experience with MBIST insertion and verification and JTAG insertion/verification.
- Proficiency in scripting for flow automation (Perl, Shell, TCL).
- Experience with multi-million-gate SoCs and IPs (networking, PLL, SerDes, etc.).
- Strong communication skills for cross-team coordination and silicon debug.
- Experience improving DFT flows and build automation (makefile/DAeRT-style enhancements).
Nice-to-have
- Experience with Mentor Tessent, Cadence Modus, and Synopsys Tetramax.
- Pattern simulation and debug using VCS and Verdi.
- Low-power DFT techniques and experience on advanced process nodes.
Education Requirements
B.Tech or M.Tech in Microelectronics, Electronics, or a related field.
About the Company
Company: eInfochips
Headquarters: Bengaluru, India
eInfochips is a product engineering and semiconductor design services company offering embedded software, SoC design and verification, testing, and IoT solutions. It operates as part of Arrow Electronics, serving clients across industries worldwide.
