Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Own Design-for-Test (DFT) for customer SoCs end-to-end, including DFT architecture, scan/ATPG, memory BIST, boundary scan, pattern validation and production test hand-off.

Work with ASIC implementation and manufacturing teams across process nodes to deliver tested, production-ready silicon.

Experience Level

Senior - minimum 3 years of hands-on DFT experience; senior-level profiles preferred.

Responsibilities

Lead and deliver DFT activities across the chip lifecycle:

• Define and implement DFT architecture (scan, memory BIST, boundary scan, I/O DFT).
• Perform scan insertion and ATPG for stuck-at, transition-delay, bridging and IDDQ fault models.
• Execute ATPG and pattern validation, including gate-level simulation and at-speed test validation.
• Develop and validate memory BIST and MBIST integration.
• Perform DFT DRC analysis and coverage debug with industry tools.
• Coordinate production test hand-off and test failure debug.
• Automate DFT flows and scripting for repeatable delivery.

Requirements

Must-have technical skills and experience:

• Minimum 3 years hands-on DFT experience.
• Practical experience with scan, ATPG, at-speed test, memory BIST and I/O DFT.
• Scan insertion and ATPG for stuck-at, transition-delay, bridging and IDDQ models; experience improving test coverage.
• Experience with Synopsys DFT Compiler / TetraMAX / SpyGlass or Siemens (Mentor) Tessent tools.
• Memory BIST experience (Tessent MBIST preferred).
• Knowledge of JTAG IEEE 1149.1, IEEE 1149.6 and IEEE 1500.
• Gate-level simulation setup and pattern validation; formal equivalence checking experience.
• Perl, Tcl and UNIX scripting for flow automation.
• End-to-end DFT flow ownership from concept through tape-out to production test hand-off.

Nice-to-have:

• Broader Siemens Tessent experience (ScanPro, TestKompress, LBIST).
• Experience at advanced nodes (7nm and below).
• Python for flow automation.

Education Requirements

BSc in Electrical Engineering from a recognized university.

About the Company

Company: Commit

Provides end-to-end ASIC and system-on-chip design and turnkey manufacturing services for fabless companies and OEMs, covering architecture, RTL-to-GDSII implementation, analog/mixed-signal design, packaging and test across process nodes (180nm–2nm) with 350+ tape-outs since 1986.