Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

The Senior DFT Engineer will design and implement design-for-test (DFT) features for ASIC blocks and SoCs, validate testability, and support integration and production test readiness. The role works within the ASICS Engineering team and collaborates with RTL, timing, verification and manufacturing teams.

Experience Level

Senior - typically 3+ years of experience in ASIC/DFT engineering. Minimum qualifications in this posting describe degree-based experience levels (see Education Requirements).

Responsibilities

Primary responsibilities include implementing and verifying DFT solutions, analyzing test coverage, and supporting timing/test debug.

• Define and implement DFT solutions (scan insertion, test modes) for blocks and SoC integration.
• Create and run ATPG and transition-delay tests; analyze and improve test coverage.
• Define test-mode timing constraints and propose timing fixes for violations.
• Simulate test vectors and validate generated patterns on RTL/netlist.
• Perform DFT rule checks and equivalence checks between RTL and netlist.
• Develop and maintain scripts and automation to support DFT flows (Perl, shell, etc.).
• Collaborate with cross-functional teams (RTL, timing, verification, manufacturing) to deliver testable designs.
• Document DFT implementation and debug findings; support handoff to ATPG/manufacturing.

Requirements

Must-have technical skills and experience for the role.

• 3+ years of ASIC/DFT experience (role-level expectation).
• In-depth knowledge of DFT concepts, scan insertion, ATPG and coverage analysis.
• Experience with transition-delay test coverage analysis and test-mode timing constraints.
• Proficiency in scripting for automation (Perl, shell, or similar).
• Experience simulating and validating test vectors on RTL/netlist.
• Knowledge of RTL lint DFT rules and ATPG tool flows.
• Strong problem-solving, multitasking, communication and teamwork skills; good English proficiency.

Nice-to-have:

• Experience with Synopsys TetraMax / DFTMax, TK, and Cadence Encounter Test.
• Familiarity with RTL lint tools (e.g., SpyGlass) and equivalence checking tools.

Education Requirements

One of the following: Bachelor's degree in Science, Engineering or related field with 2+ years of ASIC design/verification/DFT experience; OR Master's degree in Science, Engineering or related field with 1+ year of ASIC design/verification/DFT experience; OR a PhD in a related field. (These degree-based experience options were listed in the posting.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.