Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Senior DFT Engineer responsible for end-to-end design-for-test (DFT) and test infrastructure for wireless SoCs, covering architecture, implementation, verification, tapeout sign-off, silicon bring-up, and production support. Work within cross-functional tapeout teams (frontend, verification, PnR, ATE) on next-generation Wi‑Fi chips.

Relocation and visa support are available for overseas candidates.

Experience Level

Senior-level. The role expects 5+ years of DFT engineering experience.

Responsibilities

Key responsibilities include:

• Own end-to-end DFT for wireless SoCs: architecture, implementation, verification, tapeout sign-off, silicon bring-up, and production support.
• Define DFT architecture and coverage goals; optimize test quality, pattern count, power, area, and tester time/constraints.
• Architect and implement SCAN solutions (chains, sub-chains, masking, compressors/decompressors, SDCs) and ensure post-synthesis SCAN DRC clean.
• Develop and integrate at-speed test methodologies using OPCG for intra- and inter-clock domain testing.
• Implement low-power DFT techniques such as power-aware scan, clock staggering, and test-point insertion to meet ATE/package limits.
• Integrate and own MBIST and diagnostics for on-chip memories; support JTAG-based debug diagnostic flows.
• Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test-mode/pin-mux control.
• Integrate DFT for third-party hardened IPs (e.g. PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration.
• Generate and validate ATPG (stuck-at, transition, path-delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first-silicon ATE bring-up, silicon debug and yield analysis.

Requirements

Essential skills and experience. Education credentials are listed below under Education Requirements.

Must-have

• 5+ years experience as a DFT engineer on complex digital SoCs.
• Hands-on experience with scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysis.
• Strong understanding of digital design fundamentals, including RTL coding and verification.
• Post-silicon debug and silicon bring-up experience.
• Excellent verbal and written communication; strong analytical and problem-solving skills; ability to work constructively across teams under time pressure.

Nice-to-have

• Proven expertise in hierarchical DFT methodologies.
• Experience integrating hardened IP and vendor pattern integration.

Education Requirements

BSc, MSc or PhD in Electrical, Electronics or Communications Engineering, or Computer Science.

About the Company

Company: Morse Micro

Headquarters: Sydney, New South Wales, Australia

Morse Micro is an Australian fabless semiconductor company developing low-power Wi‑Fi HaLow (802.11ah) chips and SoCs for Internet of Things (IoT) applications, with global offices supporting design, silicon bring-up and production.