Senior Design Verification Engineer (SystemVerilog/UVM)
Broughton GroupJob Title
Senior Design Verification Engineer (SystemVerilog/UVM)
Role Summary
Responsible for defining and executing verification plans for complex digital and mixed-signal circuits. The role develops test cases and UVM-based testbenches, runs simulations, debugs failures, and collaborates with RTL designers to close verification tasks.
Experience Level
Senior-level. The posting does not specify a years-of-experience requirement but the title indicates a senior role (typically 7+ years in verification).
Responsibilities
Core responsibilities include:
- Define verification plans and test strategies for assigned blocks or systems.
- Design and implement testbenches and UVM testcases.
- Execute simulations, analyze results, and debug functional failures to closure.
- Collaborate with design engineers to reproduce issues and implement fixes.
- Perform coverage analysis and drive coverage closure activities.
- Document verification status, test results, and known issues.
Requirements
Must-have skills and qualifications:
- Proven experience with SystemVerilog and UVM-based verification.
- Strong debugging skills for complex digital and mixed-signal circuits.
- Experience defining verification plans and developing testcases.
- Ability to work effectively within a cross-functional engineering team and communicate results clearly.
Nice-to-have:
- Familiarity with industry simulators, coverage-driven verification, and scripting for automation.
Education Requirements
Not specified.
About the Company
Company: Broughton Group
Recruiting and staffing firm specializing in engineering and technical placements, connecting employers with candidates for roles such as hardware, firmware, embedded systems, and verification engineering.
