Senior Design Verification Engineer - PCI Express Controller IP

Job Title

Senior Design Verification Engineer - PCI Express Controller IP

Role Summary

Develop and execute verification strategies for a PCI Express controller IP. Work on a verification team to create robust testbenches, write directed and constrained-random tests, close functional coverage, and debug RTL issues to deliver high-quality IP for integration into SoCs and customer platforms.

The role requires collaboration with RTL designers, firmware and system engineers, and product management to ensure protocol compliance, performance, and silicon bring-up readiness.

Experience Level

Senior — typically 5+ years of ASIC design verification experience focused on high-speed serial protocols or controller IP.

Responsibilities

Primary responsibilities for this position include:

• Define verification plans and develop verification environments for PCIe controller IP.
• Implement UVM/SystemVerilog testbenches, directed tests, and constrained-random scenarios.
• Create and maintain protocol checkers, assertions (SVA), and functional coverage models.
• Run simulations, perform root-cause analysis, and debug functional and timing issues in RTL.
• Work with RTL engineers to drive bug fixes and coverage closure across multiple design iterations.
• Support FPGA bring-up, emulation, and pre-silicon validation activities as needed.
• Document verification results and provide regular status updates to stakeholders.

Requirements

Required technical skills and experience:

• Proven experience in design verification using SystemVerilog and UVM.
• Deep knowledge of PCI Express protocol and experience verifying PCIe controllers.
• Experience with simulation and verification tools (e.g., VCS, Questa, Incisive) and scripting (Python, Perl, TCL).
• Strong debugging skills with waveform analysis and RTL root-cause investigation.
• Experience creating assertions, protocol checkers, and functional coverage-driven verification.
• Ability to work cross-functionally and communicate verification status and technical issues clearly.

Nice-to-have:

• Experience with emulation, FPGA bring-up, formal verification, or performance validation.
• Familiarity with PCIe PHY, PHY bring-up, or system-level integration testing.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience. Advanced degrees (MS/PhD) are a plus.

About the Company

Company: Rambus

Headquarters: Sunnyvale, California, USA

Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.