Senior Design Verification Engineer — Memory Controller IP

Job Title

Senior Design Verification Engineer — Memory Controller IP

Role Summary

This senior engineering role leads functional verification efforts for memory controller IP. The engineer defines and executes verification strategies, develops testbenches and regression infrastructure, and works with architects, RTL designers, and validation/bring-up teams to ensure protocol compliance, performance, and silicon readiness.

Work is primarily within an IP/SoC verification team focused on delivering production-quality memory controller blocks.

Experience Level

Senior — typically 6+ years of experience in semiconductor design verification or equivalent industry experience.

Responsibilities

Accountable for planning and delivering verification for memory controller IP.

• Define verification plans and coverage goals for memory controller IP.
• Develop and maintain SystemVerilog/UVM testbenches, assertions, and scoreboards.
• Create, run, and scale regression suites and CI for functional and protocol testing.
• Debug RTL and testbench failures; perform root-cause analysis and drive fixes with design teams.
• Collaborate with architects, RTL designers, physical design, and bring-up engineers to resolve issues and close verification gaps.
• Mentor junior verification engineers and contribute to verification methodology improvements.

Requirements

Core technical skills and tools expected for the role.

Must-have:

• Extensive experience in functional verification of memory controller or related interface IP (typical senior-level experience).
• Proficiency in SystemVerilog and UVM for testbench and verification environment development.
• Hands-on experience with industry simulators and verification tools (e.g., VCS, Questa, or similar).
• Strong debugging skills and experience with coverage-driven verification and assertions.
• Scripting skills for automation (Python, Tcl, Perl or similar).
• Ability to work cross-functionally and communicate technical status and risks.

Nice-to-have:

• Experience with DDR/LPDDR protocol verification and memory subsystem performance validation.
• Familiarity with formal verification, emulation, or FPGA prototyping flows.
• Experience improving verification infrastructure, CI, and regression scaling.

Education Requirements

Not specified.

About the Company

Company: Rambus

Headquarters: Sunnyvale, California, USA

Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.