Senior Design Verification Engineer - FPGA

Job Title

Senior Design Verification Engineer - FPGA

Role Summary

Design Verification Engineer focused on FPGA verification for Electronic Warfare systems. The role develops and uses verification environments to validate FPGA implementations of signal processing and control functions.

The position works with cross-site engineering teams to create reusable verification IP, execute metric-driven test plans, and improve verification processes and methodologies.

Experience Level

Senior-level. The posting seeks candidates with approximately 4–6 years of relevant work experience (or equivalent practical experience).

Responsibilities

Primary duties include developing testbenches, executing verification plans, and driving measurable coverage-based verification closure.

• Develop configurable, self-checking testbenches in SystemVerilog/UVM and/or VHDL.
• Create and execute constrained-random, metric-driven test plans for FPGA verification.
• Collect, analyze, and act on functional and coverage metrics to improve test effectiveness.
• Create reusable Verification IP for use across projects and teams.
• Support verification of FPGA/ASIC designs using industry tools and simulators.
• Collaborate with engineers across multiple U.S. sites and support multi-project multitasking.
• Contribute to process and methodology improvements and mentor junior engineers when needed.

Requirements

Must-have technical skills and clearances are listed first; preferred skills follow.

• Must-have: Experience developing and using constrained-random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL.
• Experience with FPGA/ASIC verification tools (e.g., Mentor Questa or Cadence simulators).
• Ability to design and implement coverage-driven test strategies and analyze coverage data.
• Experience implementing and executing verification test plans and creating Verification IP.
• Proven ability to execute to schedule and drive tasks to closure while supporting multiple projects.
• Strong written and verbal communication and documentation skills.
• Ability to work effectively in a multi-site environment.
• Must be a U.S. Person and be able to obtain a U.S. Secret security clearance.
• Willingness to travel occasionally (<10%).

Nice-to-have / Preferred:

• Perl or Python scripting.
• C++ or Java experience.
• Experience with Git, Jira, Bitbucket.
• Digital Signal Processing and MATLAB/Simulink knowledge.
• Working knowledge of VHDL and FPGA design experience.
• Experience creating reusable Verification IP and leading small teams.
• Experience driving process improvements and mentoring colleagues.

Education Requirements

Bachelor's degree plus approximately 4–6 years of relevant work experience, or equivalent practical experience. Specific field of study was not specified in the posting.

About the Company

Company: BAE Systems

Headquarters: London, United Kingdom

Global defense, aerospace and security company delivering products and services for air, land and naval forces, advanced electronics, cyber and intelligence solutions, and space and mission systems for government and commercial customers.