Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

Design Verification Engineer responsible for verifying analog and mixed-signal IP and full-chip designs for correctness before pattern generation/mask development. The role owns verification from specification definition through post-silicon closure and customer issue resolution.

Works with architecture and cross-functional teams to define verification strategy, build UVM-based environments, and deliver signoff-quality verification results.

Experience Level

Senior - requires a minimum of 5+ years of experience in digital design verification.

Responsibilities

Primary responsibilities include ownership of verification activities, environment development, and collaboration with cross-functional teams.

• Own IP and full-chip design verification from spec definition to post-silicon verification and customer support.
• Define verification strategy and plans with regression traceability and signoff metrics.
• Develop and maintain UVM-based verification environments, testbenches, checkers, and coverage monitors.
• Verify functional and firmware scenarios at RTL and GLS levels.
• Create behavioral models for analog IPs needed for signal-chain verification.
• Perform gate-level simulations and apply formal verification methodologies where applicable.
• Debug designs and testbenches implemented in SystemVerilog, VHDL, and VAMS.
• Collaborate with Architecture, RTL, PD, DFT, Systems, Analog, Firmware, and Application teams to ensure comprehensive verification.

Requirements

Must-have technical skills and experience, followed by preferred skills.

• Must-have: 5+ years of experience in digital design verification.
• Must-have: Strong proficiency in SystemVerilog and VHDL; experience creating verification testbenches.
• Must-have: Experience developing and maintaining UVM verification environments and DV flows.
• Must-have: Experience with RTL verification and gate-level simulations; familiarity with formal verification techniques.
• Must-have: Ability to develop behavioral models for analog IP to support mixed-signal verification.
• Nice-to-have: Experience with motor-control algorithms (BLDC/BSM), commutation, sensorless control, and feedback systems.
• Nice-to-have: Familiarity with Cadence verification tools.
• Nice-to-have: Strong communication, teamwork, analytical, and time-management skills.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Electronics/ECE, Computer Science, or a related technical field as specified in the posting.

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.