Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

Join the mixed-signal silicon verification team to lead end-to-end functional verification for block- and chip-level ASIC designs. The role partners with digital and analog designers, systems, firmware/software, and manufacturing test to deliver high-quality mixed-signal IC solutions.

Work includes UVM-based testbench development, formal and hardware-accelerated verification, gate-level simulation, and software-driven validation in a collaborative engineering environment.

Experience Level

Senior-level. Typical experience guidance from the posting: Bachelor's +5 years, Master's +3 years, PhD 0+ years; significant industry experience in silicon design and/or ASIC verification is expected.

Responsibilities

Key responsibilities include designing and executing verification activities across block and chip levels and improving verification infrastructure and methodologies.

• Develop comprehensive verification plans aligned with design and system requirements.
• Perform functional verification of custom mixed-signal ASICs at block and chip level.
• Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.
• Create directed and constrained-random test suites to achieve robust functional coverage.
• Implement, analyze, and drive functional and code coverage to closure.
• Conduct failure analysis, regression triage, and debug to resolve functional and timing issues.
• Run and debug gate-level simulations, including timing and back-annotation issues.
• Develop and maintain digital and mixed-signal behavioral models to support verification.
• Support verification flow and infrastructure development, including regressions and automation.
• Collaborate cross-functionally and contribute to pre-silicon verification and post-silicon validation efforts.

Requirements

Essential skills and practical experience required for successful performance in the role.

• Significant industry experience in silicon design and/or ASIC verification.
• Proficiency with HDLs: Verilog and/or VHDL.
• Proficiency with HVLs: SystemVerilog and UVM (or equivalent HVL methodologies).
• Solid understanding of digital design principles and system architecture.
• Experience with testbench architecture, stimulus generation, regression execution, and debug.
• Experience in coverage analysis and coverage closure.
• Ability to diagnose functional and timing issues and work effectively in cross-disciplinary teams.

• Experience verifying mixed-signal ASICs and complex SoC environments.
• Knowledge of signal processing concepts relevant to mixed-signal designs.
• Experience with SystemVerilog Assertions (SVA).
• Exposure to formal verification, hardware emulation/acceleration, or software-driven verification.
• Demonstrated ability to evaluate, debug, and improve verification flows and methodologies.

Education Requirements

Degree expectation: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. The posting specifies typical experience equivalence: Bachelor's with 5+ years, Master's with 3+ years, PhD with 0+ years; equivalent practical industry experience is acceptable.

About the Company

Company: Cirrus Logic

Headquarters: Austin, TX, United States

Designer and manufacturer of high-precision analog and mixed-signal integrated circuits, specializing in audio and voice processing solutions for consumer electronics and mobile devices, including audio codecs, converters, and SoCs.