Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

On-site engineering role responsible for pre-silicon functional verification of FPGA/SoC designs at block, subsystem, and full-chip levels. The engineer will develop verification plans and reusable testbenches, run emulation and system simulations, debug failures, and work with cross-functional teams to ensure design correctness and coverage.

The team focuses on scalable verification infrastructure and improving pre-silicon validation quality informed by post-silicon findings.

Experience Level

Senior — requires 6+ years of technical experience in design validation/verification.

Responsibilities

Core responsibilities include planning, implementing, executing, and improving verification for complex silicon designs.

• Define and implement block, subsystem, and SoC verification plans and reusable verification environments.
• Develop and run constrained-random testbenches and verification IP using SystemVerilog/OVM/UVM methodologies.
• Execute emulation and system-level simulations to validate functionality, analyze performance and power, and identify defects.
• Replicate, root-cause, and debug issues found in pre-silicon environments and recommend corrective actions.
• Collaborate with architects, RTL designers, physical design, and post-silicon teams to clarify microarchitecture and resolve issues.
• Document test plans and lead technical reviews with design and architecture teams.
• Integrate security-related tests into verification plans and run regression/debug tests for security coverage.
• Maintain and improve verification infrastructure, methodologies, and coverage metrics; incorporate lessons from post-silicon validation.

Requirements

Must-have skills and experience for effective performance in this role.

• 6+ years of practical experience in pre-silicon validation/verification of complex digital designs.
• Proven experience with OVM/UVM, SystemVerilog, and constrained-random verification methodologies.
• Experience using emulation and system simulation for validation, and experience analyzing power/performance in simulation environments.
• Strong debugging and root-cause analysis skills in pre-silicon environments.
• Ability to produce and review verification plans, testbenches, and coverage metrics.
• Effective communicator with experience collaborating across architecture, RTL, and physical design teams.
• Nice-to-have: experience incorporating security validation and applying post-silicon learnings to improve pre-silicon coverage.

Education Requirements

Candidate should have a BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science Engineering, or a related technical field; the posting specifies this education together with a requirement of 6+ years of technical experience.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.