Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

Work on digital verification for IPs and subsystems within a mixed-signal semiconductor product group. The role focuses on verification planning and execution, extending verification flows, RTL and timing constraints, and interfacing with place-and-route and test teams. The position includes mentoring junior engineers and contributing to production test and silicon evaluation.

Experience Level

Senior; typically 5+ years of relevant experience in digital verification and related RTL/verification tasks.

Responsibilities

Primary duties include planning and executing verification at IP and subsystem levels, ensuring specification compliance, and supporting hand-off to physical implementation and test.

• Develop verification plans from IP/subsystem specifications and extract verification features and test cases.
• Set up and extend digital verification flows and regression frameworks, including UVM-based environments.
• Design verification components and optimized digital blocks with attention to functional, cost and low-power constraints.
• Create TCL scripts and design constraints for synthesis, DFT insertion, and static timing analysis.
• Support DFT strategy, scan insertion and ATPG generation, and production test-vector development.
• Interface with place-and-route (P&R) for digital hand-off and post-layout verification and perform silicon evaluation as needed.
• Produce high-quality documentation and develop workarounds for device errata.
• Mentor and train junior verification engineers and new graduates.

Requirements

Key qualifications and technical skills required for the role. Must-have items are listed first; preferred skills follow.

• Must-have: 5+ years experience in digital verification with practical UVM usage.
• Must-have: Hands-on experience with Verilog/SystemVerilog and RTL design/logic design/micro-architecture.
• Must-have: Experience with power product design, synthesis and timing analysis for complex analog/mixed-signal circuits.
• Must-have: Experience developing block- and top-level timing constraints for STA and P&R signoff; familiarity with synthesis scripts.
• Must-have: Knowledge of verification methodologies and platforms (functional verification, ABV, formal verification, regression frameworks, FPGA-based verification).
• Must-have: Practical knowledge of scan insertion and ATPG generation; DFT strategy support.
• Preferred: Prior experience in semiconductor domains such as PMIC or audio, with focus on mixed-signal integrated circuits.
• Preferred: Hands-on experience with TCL scripting for flows and automation.
• Ability to work independently with little supervision, propose solutions, meet tight schedules, and communicate effectively in English.
• Willingness to travel internationally on occasion at short notice.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.