Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

Lead verification activities for complex FPGA/ASIC IP, subsystems, and SoC features. Work with the verification and design teams in Penang to define verification strategy, implement SystemVerilog/UVM environments, and drive closure through tape-out.

The role focuses on ensuring functional correctness across RTL, gate-level, low-power, and system-level simulations and supporting silicon bring-up and root-cause analysis when required.

Experience Level

Senior - typically requires 5+ years of ASIC/FPGA functional verification experience.

Responsibilities

Core responsibilities include the following:

• Lead verification from specification through tape-out for IP, subsystems, and SoC features.
• Develop verification strategies, test plans, and closure criteria aligned with product requirements.
• Architect and implement scalable SystemVerilog/UVM verification environments, checkers, assertions, scoreboards, and coverage models.
• Develop constrained-random and directed tests to meet functional and code coverage goals.
• Debug design, testbench, simulation, and integration issues across RTL, GLS, low-power, and system-level flows.
• Collaborate with architects, design, firmware, and validation teams to resolve issues and integrate features.
• Drive verification sign-off activities: coverage closure, regression analysis, and risk assessment.
• Mentor junior verification engineers and contribute to verification methodology and reusable infrastructure.
• Support silicon bring-up and perform root-cause analysis as needed.

Requirements

Must-have technical skills and experience:

• Minimum 5 years of ASIC/FPGA functional verification experience.
• Strong expertise in SystemVerilog and UVM.
• Experience building verification environments: drivers, monitors, scoreboards, assertions, and coverage models.
• Strong debugging skills across RTL, gate-level, and system-level simulations.
• Experience with industry-standard simulators and verification tools.
• Strong scripting skills (Python, Perl, Shell, or equivalent).

Nice-to-have:

• Experience with PCIe, USB, MIPI CSI/DSI, Ethernet, SerDes, or other high-speed protocols.
• Experience with low-power verification methodologies (UPF/CPF).
• Experience with GLS, timing analysis, and post-silicon debug.
• Knowledge of FPGA architecture and programmable logic devices.
• Prior experience leading verification for a major IP or subsystem and mentoring teams.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.