Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

Join the silicon engineering verification team responsible for verifying complex FPGAs and SOC-level integrations. The role focuses on building and productizing verification environments, driving coverage-directed verification, and integrating IP- and subsystem-level testbenches into SOC-level flows.

This position works closely with design, architecture, software/firmware, and IP teams to ensure tape-out readiness and improve verification methodology and tooling.

Experience Level

Senior — requires a seasoned verification engineer. The posting requests at least 6+ years of design verification experience, with 2+ years leading complex IP verification efforts.

Responsibilities

Primary responsibilities include verification planning, environment development, and cross-team integration to achieve tape-out quality.

• Create IP- and subsystem-level verification plans and define coverage goals.
• Design and implement UVM-based, highly reusable testbenches, sequences, and verification infrastructure.
• Integrate complex multi-instance VIPs and subsystem testbenches into SOC-level verification suites.
• Develop coverage-driven and directed tests to meet verification targets.
• Verify firmware interactions, boot-up, power-cycling, and HW/FW integration aspects of the SOC.
• Collaborate with design, architecture, SW/FW, and IP delivery teams to resolve issues and verify system behavior.
• Contribute to tool deployment, methodology improvements, and verification automation.
• Lead verification efforts for complex IP blocks and mentor junior engineers as needed.

Requirements

Must-have technical skills and experience required for successful performance in the role.

• Minimum 6+ years of design verification (DV) experience; 2+ years leading complex IP verification.
• Proven experience in full ASIC verification flows from concept to tape-out.
• Advanced knowledge and hands-on use of SystemVerilog and UVM methodology.
• Experience developing portable, reusable verification infrastructure and integrating VIPs at IP and SOC levels.
• Experience verifying firmware used for SOC functions and validating HW/FW interactions.
• Strong communication, problem solving, and teamwork skills.
• Ability to work in a dynamic, multi-functional engineering organization and drive verification to closure.
• Nice-to-have: hands-on verification of PCIe, Ethernet, USB IPs; AMBA bus verification experience; exposure to low-power design and UPF integration.

Education Requirements

BS or MS in Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree; equivalent practical experience will be considered.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.