Senior Design Engineer - High Speed Cache

Job Title

Senior Design Engineer - High Speed Cache

Role Summary

Design and implement a high-performance L2 cache unit serving AI processing elements. The role sits on the hardware/ASIC design team and focuses on cache controller, coherency, and low-power logic for multicore SoCs.

The position emphasizes RTL and physical-aware design practices to meet performance, power, and timing targets.

Experience Level

Senior level. The posting requests 2–4 years of relevant experience; exceptional candidates with less experience may be considered.

Responsibilities

Key responsibilities include:

• Design and implement L2 cache and cache controller logic for high-performance AI processors.
• Develop and verify cache coherency protocols and cache hierarchy behavior.
• Create RTL in Verilog/SystemVerilog and support synthesis and static timing closure.
• Perform STA, CDC analysis, linting, and timing-driven design iterations.
• Apply low-power and deep-submicron design techniques to meet power and performance targets.
• Collaborate with microarchitecture, verification, and physical design teams to integrate cache into multicore SoC.
• Optimize cache/memory interfaces for bandwidth, latency, and coherence.

Requirements

Must-have technical skills and experience:

• 2–4 years of relevant ASIC/SoC design experience (consideration for exceptional candidates with lower experience).
• Strong understanding of computer architecture and multicore processor pipelines.
• Experience with cache controller design and cache coherency protocols.
• RTL design experience (Verilog/SystemVerilog), synthesis, STA, CDC, and lint flows.
• Experience with logic design in deep-submicron technologies and low-power techniques.

Nice-to-have:

• Familiarity with ARM and x86 processor designs.
• Programming and scripting skills (C, Perl, shell, Python, AWK).

Education Requirements

Not specified.

About the Company

Company: Tachyum

Headquarters: Sunnyvale, CA, USA

Tachyum develops Prodigy, a universal processor that combines CPU, GPU, and TPU capabilities to deliver high-performance, energy-efficient computing for AI, HPC, and cloud data centers. The company focuses on ultra-low power, hyperscale deployments and operates offices in the United States and Slovakia.