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Senior Debug Verification Engineer

Altera
September 30, 2026
Full-time
On-site
San Jose, California, United States
$149,100 - $215,000 USD yearly
Verification Jobs, Level - Senior

Job Title

Senior Debug Verification Engineer

Role Summary

Responsible for verification of design-for-debug architectures and full-chip/system functional verification using UVM and related methodologies. Works with design, software, and architecture teams to define verification strategies, create testbenches and testcases, and validate system performance prior to silicon.

Experience Level

Senior - requires 8+ years of experience in complex ASIC design and/or verification per the posting.

Responsibilities

Deliver verification coverage for debug architecture and full-chip/system designs; plan and execute verification activities and coordinate across teams.

  • Pre-silicon system verification for SoC, FPGA, and full-chip designs.
  • Create testcases and testbenches using UVM methodology.
  • Define verification strategies, methodologies, and test plans to achieve effective coverage.
  • Verify Design-for-Debug features (JTAG, high-speed USB, PCIe-based debug, internal signal visualization).
  • Coordinate verification efforts with Design, Software, and Architecture teams.
  • Use system-level application tests to verify performance and identify shortcomings.
  • Use emulation platforms when applicable.

Requirements

Must-have technical skills and experience; followed by desirable additions.

  • Must-have: 8+ years working on complex ASIC designs and/or verification.
  • Must-have: 8+ years with SystemVerilog.
  • Must-have: 8+ years with UVM verification methodology and familiarity with formal verification methods.
  • Must-have: Experience scripting in Linux/Unix; proficiency in Perl and/or Python is expected.
  • Must-have: Experience with Design-for-Debug architecture and its verification (JTAG, PCIe/USB debug, visualization of internal signals).
  • Must-have: Strong communication skills and ability to work with distributed teams.
  • Nice-to-have: Experience with ARM and RISC debug architectures.
  • Nice-to-have: Prior work with UltraSoC or Tessent Embedded Analytics Debug Architecture.
  • Nice-to-have: Experience with emulation.

Education Requirements

Not specified.


About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.

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Date Posted: 2026-09-29