Senior Debug Verification Engineer
AlteraJob Title
Senior Debug Verification Engineer
Role Summary
Responsible for verification of debug architectures and related design-for-debug features for SoC/FPGA/full-chip projects. Work with design, software, and architecture teams to define verification strategy, create UVM testbenches and test cases, and validate system-level debug functionality and performance.
Role focuses on pre-silicon system verification and coordination across cross-functional teams to achieve full coverage of debug-related features and interfaces.
Experience Level
Senior — requires substantial relevant experience; posting specifies 8+ years of ASIC/verification experience.
Responsibilities
Primary responsibilities include verification planning, testbench development, and cross-functional coordination to validate debug architectures and system behavior.
- Define verification strategy, methodology, and test plans for full-chip/system verification.
- Develop UVM testbenches and create testcases to validate debug architectures and system functionality.
- Perform pre-silicon system verification for SoC, FPGA and full-chip designs.
- Verify Design-for-Debug features (e.g., JTAG, high-speed USB, PCIe debug paths, internal signal visualization).
- Coordinate with Design, Software, and Architecture teams to close coverage and resolve issues.
- Use system-level workloads to validate performance and identify shortfalls; support emulation where applicable.
Requirements
Must-have technical skills and experience; followed by desirable additions.
- Must-have: 8+ years working on complex ASIC designs and/or verification.
- Must-have: 8+ years with SystemVerilog and UVM methodology; experience with formal verification methods.
- Must-have: Experience scripting in Linux/Unix environments; proficiency in Perl and/or Python is expected or desirable.
- Must-have: Strong communication skills and ability to work with geographically distributed teams.
- Nice-to-have: Experience with ARM and RISC debug architectures.
- Nice-to-have: Prior exposure to UltraSoC or Tessent Embedded Analytics debug architectures.
- Nice-to-have: Experience with emulation platforms.
Education Requirements
Not specified.
About the Company
Company: Altera
Headquarters: Bengaluru, Karnataka, India
Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.
