Senior CAD Manager

Job Title

Senior CAD Manager

Role Summary

Lead the Central Engineering CAD organization to support and improve automated digital design flows and methodologies across Marvell business units. The role focuses on tool and flow deployment, resolving synthesis, P&R, STA and power-integrity issues, and collaborating with EDA vendors and design teams to enable faster time-to-market and first-pass silicon success.

Experience Level

Senior-level — requires 12+ years of experience in physical design and flow development.

Responsibilities

Primary responsibilities include:

• Lead digital flow and methodology support for block and SoC designs across multiple business units.
• Develop, deploy, and maintain automated design flows and CAD tools; ensure broader adoption through quality documentation.
• Diagnose and resolve issues in synthesis, place & route, static timing analysis, and timing closure.
• Address power integrity, EM/IR, power-intent implementation, multiple power-domain strategies, and related routability concerns.
• Design and evaluate floorplanning, power grid strategies, and clock synthesis schemes; correlate upstream and downstream flows.
• Collaborate with EDA vendors and methodology experts to optimize tool usage and flows.
• Automate flows and solutions using Tcl scripting and provide technical leadership and project management to meet delivery milestones.

Requirements

Must-have vs. nice-to-have qualifications:

• Must-have: 12+ years of experience in physical design and flow development; experience with 16nm or below (preferably 7nm and 5nm); familiarity with FinFET, dual patterning, and ULV challenges; experience supporting RTL-to-GDSII flows; expertise in timing closure, synthesis, and constraint debugging; proficiency in Tcl scripting; experience with floorplanning, power grid design, routability, clock synthesis, SI, EM/IR, DRC, and power intent; strong problem-solving, communication, and project management skills.
• Nice-to-have: Knowledge of DFT; working knowledge of SoC architecture, RTL, pre-silicon functional verification; experience with logical equivalence checks and CLP flows.

Education Requirements

B.Tech or M.Tech in Electrical Engineering or Computer Science (B.Tech/M.Tech in EE/CS) as specified in the posting. The role also specifies 12+ years of relevant experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.