Senior CAD Engineer - Physical Verification

Job Title

Senior CAD Engineer - Physical Verification

Role Summary

Develop and maintain physical verification tools, flows, and methodologies to support DRAM, HBM, NAND, and emerging memory products. The role partners with process, design, layout, modeling, and verification teams to define signoff strategies and resolve production verification issues.

Lead technical projects, improve verification quality and performance, and provide training, documentation, and production support for global design teams.

Experience Level

Senior - typically requires 5+ years of industry experience in CAD, EDA, or semiconductor design.

Responsibilities

Key responsibilities include developing verification rule decks and automating verification flows, collaborating across engineering teams, and driving verification roadmap items.

• Develop and maintain physical verification tools, flows, and methodologies for DRAM, HBM, NAND, and emerging memory products.
• Develop, debug, qualify, and release Siemens Calibre DRC and LVS rule decks using SVRF.
• Translate process design rules into verification checks; define test cases, coverage criteria, and regression methods.
• Partner with process, design, layout, modeling, and verification teams to define signoff strategies and resolve verification issues.
• Guide design teams on verification methodologies, waivers, and debugging; provide training, documentation, and production support.
• Evaluate EDA technologies to improve verification quality, performance, and capacity.
• Automate verification setup, execution, and reporting, including AI-assisted analysis and debugging.
• Lead technical projects and contribute to the physical verification roadmap.

Requirements

Must-have technical skills and experience.

• 5+ years industry experience in CAD, EDA, or semiconductor design.
• Experience with DRC and LVS physical verification, IC layout, and process design rules.
• Ability to interpret design-rule requirements and resolve complex verification issues in production flows.
• Proficiency in Python and at least one additional language (SKILL, Tcl, Perl, C, or C++).
• Linux/Unix and shell scripting experience.
• Strong CMOS and VLSI fundamentals; practical debugging and clear cross-team communication skills.

Nice-to-have:

• Experience developing and qualifying Calibre DRC and LVS rule decks in SVRF, using nmDRC, nmLVS, and RVE.
• Knowledge of layout-dependent effects, electrical rule checking (ERC/PERC), antenna, and density checks.
• Experience optimizing rule-deck coverage, runtime, and memory usage.
• Experience with Cadence Virtuoso, SKILL, or Cadence physical verification tools.
• Experience applying AI/ML, large language models, or agentic AI to engineering workflows.
• Experience with source control, automated testing, and release management.
• Knowledge of DRAM, HBM, NAND, or emerging memory development.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent practical experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.