Senior CAD Engineer - Floor Plan
Intel CorporationJob Title
Senior CAD Engineer - Floor Plan
Role Summary
Senior CAD Engineer responsible for deploying and maintaining Design Planning and RTL-to-Floorplan methodologies and automation for CPU IP development. The role partners with CPU Physical Design, Architecture, RTL, and CAD teams to deliver scalable, production-quality flows, tooling, and productivity improvements across multiple CPU programs and technology nodes.
Experience Level
Senior-level. The role typically requires 4+ years of industry experience in CAD/Design Automation and physical design methodology.
Responsibilities
Primary responsibilities focus on methodology ownership, automation, tool support, and cross-team coordination to improve RTL-to-floorplan and design planning workflows.
- Own and support deployment of Design Planning and RTL-to-Floorplan methodologies across CPU IP programs.
- Design, maintain, and enhance automation frameworks for RTL-to-Floorplan, floorplan generation, early PPA estimation, and routability/congestion analysis.
- Provide technical support to Physical Design teams: debug flows, tools, and methodology issues.
- Drive improvements in flow quality, robustness, scalability, and usability.
- Create dashboards, reporting infrastructure, and analytics to track methodology health, usage, and quality metrics.
- Work with implementation teams and EDA vendors to evaluate and integrate new tool capabilities and releases.
- Enable methodology correlation and consistency across projects and technology nodes; produce documentation and training materials.
- Explore Machine Learning, Generative AI, and agentic AI techniques to assist methodology deployment, flow debugging, and productivity.
Requirements
Must-have technical skills and experience to perform the role effectively; preferred items are listed separately.
- 4+ years industry experience in CAD engineering, design automation, physical design methodology, EDA tool development, or physical design infrastructure.
- Strong understanding of physical design flows, RTL-to-Floorplan methodologies, design planning concepts, floorplanning fundamentals, and PPA analysis.
- Experience supporting and deploying implementation tools such as Synopsys Fusion Compiler, ICC2, Cadence Innovus, or equivalent platforms.
- Production-quality CAD automation and methodology framework development experience.
- Strong software and scripting skills: Python, Tcl, and shell scripting.
- Preferred: experience supporting CPU core/cache/fabric IP, advanced technology nodes (e.g., Intel 18A/14A, TSMC N3/N2), distributed compute/cloud-based CAD environments, and familiarity with ML/LLMs for EDA applications.
- Preferred: working knowledge of timing, power, congestion, routability, and signoff considerations relevant to design planning.
Education Requirements
M.Tech or MS in Electrical Engineering, Computer Engineering, Computer Science, VLSI, or a related technical field (as listed in the minimum qualifications).
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
