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Senior CAD Engineer, ASIC Development Infrastructure, RTL Design

KGS
May 29, 2026
Full-time
On-site
Boise, Idaho, United States
$159,200 - $215,300 USD yearly
EDA Jobs, Level - Senior

Job Title

Senior CAD Engineer, ASIC Development Infrastructure, RTL Design

Role Summary

Senior CAD Engineer on an ASIC development team responsible for building and maintaining RTL-to-GDSII tool flows and infrastructure. The role supports Design, Verification, Physical Design, Emulation, and IT teams to enable reliable, automated semiconductor design workflows.

Experience Level

Senior — typically 5+ years supporting CAD infrastructure for ASIC development.

Responsibilities

Own, deploy, and improve the ASIC tool flows and related infrastructure to accelerate and stabilize chip design work.

  • Design and maintain RTL-to-GDSII flows: RTL generation, simulation, synthesis, place & route, timing analysis, DRC/LVS, and sign-off.
  • Deploy and configure vendor EDA tools (Synopsys, Cadence, Mentor/Siemens) across compute infrastructure.
  • Develop automation, CI/CD pipelines, and regression systems to reduce manual effort and improve consistency.
  • Troubleshoot tool failures; engage vendors to resolve bugs, performance issues, and licensing problems.
  • Work with IT to optimize compute and storage for engineering workloads.
  • Create and maintain documentation, flow methodologies, and best practices.
  • Apply AI-assisted tools to accelerate troubleshooting and monitoring of design flows.

Requirements

Must-have technical skills and experience required to perform the role; preferred items noted separately.

  • Must-have: Proficiency in Python and Embedded C.
  • Must-have: Experience with version control systems and implementing CI/CD pipelines.
  • Must-have: Ability to write and understand Verilog and SystemVerilog.
  • Must-have: Experience deploying and supporting ASIC tools (simulation, synthesis, place & route, license management).
  • Must-have: Proven experience leading technical initiatives and delivering key engineering infrastructure.
  • Must-have: 5+ years building and supporting CAD infrastructure for ASIC development.
  • Nice-to-have: RTL coding and debug experience; performance, power, and area analysis.
  • Nice-to-have: Familiarity with additional scripting (bash), dashboarding tools, and documentation automation.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field is required. A Master’s degree or Ph.D. in Electrical Engineering or a related field is preferred. The posting references degrees in technical/engineering fields but does not state an explicit equivalency clause.


About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.

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Date Posted: 2026-05-29