Senior ASIC Verification Engineer

Job Title

Senior ASIC Verification Engineer

Role Summary

Senior verification engineer on the Memory Management Unit (MMU) within the GPU ASIC Verification organization. The role focuses on defining verification scope, building verification infrastructure, implementing test and coverage plans, and validating design correctness.

Your work will contribute to NVIDIA GPUs used across graphics, high-performance computing, and AI products.

Experience Level

Senior-level. The posting specifies 8+ years of relevant work or research experience.

Responsibilities

Primary responsibilities include planning and executing verification for the Memory Management Unit and advancing verification methodology.

• Define verification scope for MMU features and micro-architecture.
• Design and implement verification infrastructure: testbenches, bus functional models (BFMs), checkers, and monitors.
• Develop and execute test plans and coverage plans; drive coverage closure.
• Verify design correctness via simulation, debug failures, and support root-cause analysis.
• Collaborate with architects, designers, and software engineers across sites to align verification and design goals.
• Plan and evolve testbench strategy and verification methodology.

Requirements

Must-have technical skills and experience for the role.

• Proven experience with SystemVerilog and developing reusable verification components.
• Proficiency in C and/or C++ for verification tasks.
• Experience with constrained-random testing, functional coverage, and assertion-based verification.
• Familiarity with object-oriented programming concepts applied to verification.
• Exposure to computer architecture, ASIC design, and verification methodology.
• Experience with simulation and debug tools (examples: VCS, IES, Debussy, GDB).
• Strong test planning, coverage closure, debugging, problem-solving, and interpersonal skills.

Nice-to-have:

• Understanding of memory subsystem micro-architecture, cache topologies and policies, memory management, interconnects, or arbiter designs.
• Experience with UVM, SystemVerilog scoreboards/checkers, semiformal verification.
• Scripting experience (Python or Perl).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or a related technical field — or equivalent practical experience.

Additional Information

Base salary ranges by level: Level 4 — 168,000 USD to 264,500 USD (yearly); Level 5 — 196,000 USD to 310,500 USD (yearly). Candidates may also be eligible for equity and benefits.

Applications for this job will be accepted at least until 2026-08-31.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.