Senior ASIC Verification Engineer

Job Title

Senior ASIC Verification Engineer

Role Summary

Senior ASIC Verification Engineer on the HPE Networking Silicon team responsible for block- and subsystem-level verification of high-speed networking ASICs used in routers and switches. The role focuses on building and maintaining verification environments, executing test plans, and driving coverage closure from specification to validated netlist.

Hybrid role based in Sunnyvale, CA with an expectation of approximately 2 days per week in the office.

Experience Level

Senior — typically 10+ years of ASIC/SoC verification experience with demonstrated ownership from test planning through coverage closure.

Responsibilities

Primary duties include verification planning, environment development, simulation and debug, and cross-team issue resolution.

• Own block- and subsystem-level verification: create test plans, implement tests, and drive coverage closure.
• Develop, enhance, and maintain UVM/SystemVerilog verification environments (agents, sequences, scoreboards, virtual sequences, register models).
• Perform constraint-driven random testing, collect functional coverage, and implement SVA assertions.
• Run and analyze simulations using tools such as Cadence Xcelium, Synopsys VCS, or Mentor Questa; debug waveforms and failures.
• Collaborate with RTL, architecture, firmware, and validation teams to identify and resolve design issues and to ensure high-quality ASIC/SoC deliverables.

Requirements

Must-have technical skills and relevant preferred experience.

• Must-have: 10+ years of ASIC/SoC verification experience with ownership from test plan to coverage closure.
• Must-have: Strong SystemVerilog and UVM skills; experience building verification environments from scratch.
• Must-have: Deep understanding of randomization, constraints, functional coverage, and SVA assertions.
• Must-have: Hands-on experience with simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debug.
• Must-have: Experience in test planning, coverage analysis, and debugging complex SoC designs.
• Preferred: Experience with networking ASICs (packet processing, forwarding engines, fabric interfaces), high-speed interconnects, or scheduling pipelines.
• Preferred: Exposure to emulation/hardware acceleration, post-silicon bring-up, coverage analytics, CI/regression flows (e.g., Jenkins), UPF or formal verification methods.

Education Requirements

Not specified.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.