Senior ASIC RTL Integration and Netlisting Engineer
NVIDIAJob Title
Senior ASIC RTL Integration and Netlisting Engineer
Role Summary
Responsible for RTL integration, synthesis, and delivery of physical netlists for high-frequency and low-power CPUs, GPUs, and SoCs at block, cluster, and full-chip levels. Works with physical design, verification, and EDA teams to ensure netlist quality and readiness for downstream flows.
Core mission: produce correct, performant, and verifiable gate-level netlists across milestones, including equivalence checking, netlist quality checks, CDC checks, and MTBF analysis.
Experience Level
Senior — experience guidance: typically 8+ years for BS or equivalent experience, or 5+ years with an MS (see Education Requirements).
Responsibilities
Primary responsibilities include integration, verification, and delivery of synthesis and netlist artifacts and checks.
- Lead RTL integration and synthesis activities and manage netlist deliverables across project milestones.
- Drive formal equivalence checking and gate-level netlist verification to ensure functional parity with RTL.
- Perform netlist quality checks related to power, testability, and structural completeness.
- Perform asynchronous interface reviews, clock-domain crossing checks, and MTBF analysis.
- Collaborate with physical design teams on timing, power convergence, and design constraints.
- Develop and maintain scripts/tools to automate netlist checks and integration flows.
Requirements
Must-have technical skills and experience required for this role.
- Deep understanding of RTL structure, hierarchy, and integration infrastructures.
- Hands-on experience with logic synthesis and associated verification flows such as equivalence checking.
- Experience in gate-level netlist verification including power and testability considerations.
- Proven expertise with industry-standard EDA tools for synthesis, formal, and verification.
- Ability to work across cross-functional teams and deliver netlists on project milestones.
Nice-to-have:
- Strong knowledge of clock-domain crossings, asynchronous interfaces, and MTBF analysis.
- Familiarity with physical design flows, timing/power convergence, and constraint creation.
- Proficiency in scripting/programming (Python, Tcl) and familiarity with AI-assisted coding tools.
Education Requirements
BS in Electrical Engineering or Computer Engineering (or equivalent practical experience) with ~8+ years in RTL integration/netlisting, or MS in Electrical/Computer Engineering (or equivalent practical experience) with ~5+ years in the domain. The posting allows equivalent practical experience in place of a degree.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
