Senior ASIC RTL Design Engineer

Role Summary

As a Senior ASIC RTL Design Engineer, you will be part of the SBIO front-end design and integration team at Advanced Micro Devices. Your main responsibility will involve collaborating with architecture, IP design, physical design, and product engineering teams to develop high-quality IP for SOC products and ensure first-pass silicon success.

Experience Level

This position requires a strong background in digital design and processor architecture, as well as experience in verification. Candidates should be adept at solving complex technical challenges and should communicate effectively in cross-site or distributed teams.

Key Responsibilities

Responsibilities include:

• Designing RTL for high-speed digital blocks, including clock, reset, and power management features.
• Architecting and implementing low-power RTL techniques.
• Integrating IP blocks at the subsystem level and resolving design integration issues.
• Managing clock-domain crossing and linting activities.
• Collaborating with teams to incorporate feedback across disciplines.
• Contributing to architecture and microarchitecture documentation.
• Providing clear status updates and participating in team problem-solving activities.

Requirements

Ideal candidates should possess:

• A background in digital IP/ASIC design and Verilog-based RTL development.
• Familiarity with the full IP design cycle, from requirements to validation.
• An understanding of RTL verification and design quality checks.
• Experience with EDA tools and low-power design methodologies.
• Knowledge of scripting languages, such as Python or Perl.
• The ability to create clear technical documentation in English.
• Knowledge of semiconductor engineering terminology and digital design concepts.
• Experience with functional design verification is preferred.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field is required for this role.