Senior ASIC Physical Design Engineering Technical Lead

Job Title

Senior ASIC Physical Design Engineering Technical Lead

Role Summary

Lead full-chip and hierarchical physical implementation for advanced-node ASICs, focusing on floorplanning, power and clock architectures, place-and-route, timing closure, and signoff. Work cross-functionally with RTL, DFT, package, foundry and EDA vendors to optimize performance, power and die size.

Position based in Durham, NC within the physical design/implementation organization.

Experience Level

Senior-level. See Education Requirements for degree-linked years-of-experience guidance.

Responsibilities

Accountabilities include full-chip planning, implementation, and cross-team integration.

• Define and execute full-chip floorplans considering architecture, IP placement, foundry guidelines and package requirements.
• Perform hierarchical implementation: partitioning, pin assignment, clock planning and bump planning.
• Implement RTL-to-GDSII flow: floorplan, power-grid planning, place and route, static timing analysis, power integrity, physical verification and equivalence checks.
• Design and optimize full-chip clock networks (mesh or Flex-HTree) for timing and performance.
• Collaborate with RTL, DFT, implementation, package, foundry and EDA vendors to enable signoff-quality flows.
• Analyze and improve tool flows and methodologies to increase efficiency and quality.
• Apply low-power design methodologies and validate power intent through the implementation flow (UPF).
• Leverage AI and automation tools to improve productivity and flow quality.

Requirements

Must-have technical skills and domain experience.

• Extensive physical design experience with RTL-to-GDSII implementation and tapeouts at advanced process nodes (7nm/5nm/3nm or below).
• Hands-on use of EDA tools such as Innovus, Tempus/PrimeTime, RedHawk/Voltus, Calibre or Pegasus.
• Proven experience with floorplanning, power-grid planning, partitioning, pin-assignment, and timing closure.
• Experience in full-chip clocking strategies and convergence for performance optimization.
• Practical knowledge of low-power design flows and UPF-based methodologies.
• Ability to work cross-functionally with RTL/DFT/implementation teams, foundry and IP vendors, and post-silicon validation teams.

Nice-to-have:

• Experience with hierarchical design flows and advanced power integrity analysis.
• Strong STA knowledge: constraint definition, corners, exceptions.
• Familiarity with Python scripting and effective use of AI tools for flow automation.

Education Requirements

Degrees specified: Bachelor's, Master's or PhD in Electrical Engineering with degree-linked experience expectations: BS +12 years, MS +8 years, PhD +5 years of physical design experience. Equivalent practical experience is acceptable.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).