Senior ASIC Physical Design Engineering Technical Lead

Job Title

Senior ASIC Physical Design Engineering Technical Lead

Role Summary

Lead full-chip physical design and implementation for advanced-node ASICs. Own floorplanning, hierarchical implementation, timing and power closure, and physical verification while coordinating across system, package, RTL, DFT, EDA vendors, foundry and IP partners.

Experience Level

Senior-level. This role requires significant, hands-on ASIC physical design experience and leadership in implementation and methodology.

Responsibilities

Deliver and lead physical design activities from floorplan through signoff and drive methodology and tool improvements.

• Define and execute full-chip floorplan based on architecture, foundry rules and IP placement constraints.
• Collaborate with system and package teams to incorporate requirements into the floorplan and implementation.
• Perform hierarchical implementation: partitioning, pin assignment, clock planning, bump planning and timing closure.
• Execute RTL-to-GDSII flow: floorplan, power-grid planning, place-and-route, static timing analysis, power integrity analysis, physical verification and equivalence checks.
• Optimize performance, power and die size through design and implementation trade-offs.
• Work with RTL, DFT, implementation engineers and EDA vendors to enable and tune design flows and signoff methodologies.
• Coordinate with foundry and standard-cell/IP vendors to define and validate signoff criteria; iterate based on post-silicon feedback.
• Analyze tool flows and methodologies; identify gaps and implement incremental or transformative improvements.
• Apply low-power design practices (UPF) and leverage AI tools to improve productivity and automation.

Requirements

Core technical requirements and preferred skills.

• Must-have: Extensive hands-on physical design experience including RTL-to-GDSII tapeouts at advanced process nodes (7nm/5nm/3nm or below).
• Must-have: Practical experience with full-chip clocking (clock mesh, Flex-HTree or equivalent) and hierarchical implementation flows.
• Must-have: Proficiency with industry EDA tools such as Innovus, Tempus/PrimeTime, RedHawk/Voltus and Calibre/Pegasus.
• Must-have: Strong skills in floorplanning, power-grid planning, place-and-route, static timing analysis, power integrity and physical verification.
• Must-have: Experience applying UPF-based low-power design methodologies.
• Must-have: Experience working with foundry and standard-cell/IP vendors and integrating vendor signoff guidance into flows.
• Nice-to-have: Experience with hierarchical design convergence, timing closure techniques, and custom chip-level H-Tree or mesh clock strategies.
• Nice-to-have: Python skills and experience using AI tools to improve design productivity, including prompt-based workflows.
• Nice-to-have: Experience incorporating post-silicon validation feedback into signoff and flow adjustments.

Education Requirements

Bachelor's, Master's or PhD in Electrical Engineering. Experience expectations provided in the posting: Bachelor's-level candidates typically have ~12+ years of physical design experience, Master's-level ~8+ years, PhD-level ~5+ years of physical design experience.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).